diff options
author | johpow01 <john.powell@arm.com> | 2020-10-02 13:41:11 -0500 |
---|---|---|
committer | John <john.powell@arm.com> | 2021-02-25 22:01:59 +0000 |
commit | 873d4241e324cf619e68880aaa9f890296cdba8b (patch) | |
tree | 3349939ea0c29272df21c5491a6071d44901c555 /include | |
parent | 8909fa9bbf159f12cec0a06a3e57bc32a65953b8 (diff) | |
download | trusted-firmware-a-873d4241e324cf619e68880aaa9f890296cdba8b.tar.gz |
Enable v8.6 AMU enhancements (FEAT_AMUv1p1)
ARMv8.6 adds virtual offset registers to support virtualization of the
event counters in EL1 and EL0. This patch enables support for this
feature in EL3 firmware.
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I7ee1f3d9f554930bf5ef6f3d492e932e6d95b217
Diffstat (limited to 'include')
-rw-r--r-- | include/arch/aarch32/arch.h | 10 | ||||
-rw-r--r-- | include/arch/aarch32/arch_helpers.h | 3 | ||||
-rw-r--r-- | include/arch/aarch64/arch.h | 69 | ||||
-rw-r--r-- | include/arch/aarch64/arch_features.h | 8 | ||||
-rw-r--r-- | include/arch/aarch64/arch_helpers.h | 4 | ||||
-rw-r--r-- | include/lib/extensions/amu.h | 22 | ||||
-rw-r--r-- | include/lib/extensions/amu_private.h | 10 |
7 files changed, 108 insertions, 18 deletions
diff --git a/include/arch/aarch32/arch.h b/include/arch/aarch32/arch.h index c30073b8c7..54ec009534 100644 --- a/include/arch/aarch32/arch.h +++ b/include/arch/aarch32/arch.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -116,6 +116,9 @@ #define ID_PFR0_AMU_SHIFT U(20) #define ID_PFR0_AMU_LENGTH U(4) #define ID_PFR0_AMU_MASK U(0xf) +#define ID_PFR0_AMU_NOT_SUPPORTED U(0x0) +#define ID_PFR0_AMU_V1 U(0x1) +#define ID_PFR0_AMU_V1P1 U(0x2) #define ID_PFR0_DIT_SHIFT U(24) #define ID_PFR0_DIT_LENGTH U(4) @@ -653,7 +656,7 @@ #define PAR_ADDR_MASK (BIT_64(40) - ULL(1)) /* 40-bits-wide page address */ /******************************************************************************* - * Definitions for system register interface to AMU for ARMv8.4 onwards + * Definitions for system register interface to AMU for FEAT_AMUv1 ******************************************************************************/ #define AMCR p15, 0, c13, c2, 0 #define AMCFGR p15, 0, c13, c2, 1 @@ -712,6 +715,9 @@ #define AMEVTYPER1E p15, 0, c13, c15, 6 #define AMEVTYPER1F p15, 0, c13, c15, 7 +/* AMCR definitions */ +#define AMCR_CG1RZ_BIT (ULL(1) << 17) + /* AMCFGR definitions */ #define AMCFGR_NCG_SHIFT U(28) #define AMCFGR_NCG_MASK U(0xf) diff --git a/include/arch/aarch32/arch_helpers.h b/include/arch/aarch32/arch_helpers.h index 82efb188a4..726baf596e 100644 --- a/include/arch/aarch32/arch_helpers.h +++ b/include/arch/aarch32/arch_helpers.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -303,6 +303,7 @@ DEFINE_COPROCR_RW_FUNCS(dacr, DACR) /* Coproc registers for 32bit AMU support */ DEFINE_COPROCR_READ_FUNC(amcfgr, AMCFGR) DEFINE_COPROCR_READ_FUNC(amcgcr, AMCGCR) +DEFINE_COPROCR_RW_FUNCS(amcr, AMCR) DEFINE_COPROCR_RW_FUNCS(amcntenset0, AMCNTENSET0) DEFINE_COPROCR_RW_FUNCS(amcntenset1, AMCNTENSET1) diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h index 2cdc7b2303..b86a13ed30 100644 --- a/include/arch/aarch64/arch.h +++ b/include/arch/aarch64/arch.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -161,6 +161,9 @@ #define ID_AA64PFR0_EL3_SHIFT U(12) #define ID_AA64PFR0_AMU_SHIFT U(44) #define ID_AA64PFR0_AMU_MASK ULL(0xf) +#define ID_AA64PFR0_AMU_NOT_SUPPORTED U(0x0) +#define ID_AA64PFR0_AMU_V1 U(0x1) +#define ID_AA64PFR0_AMU_V1P1 U(0x2) #define ID_AA64PFR0_ELX_MASK ULL(0xf) #define ID_AA64PFR0_GIC_SHIFT U(24) #define ID_AA64PFR0_GIC_WIDTH U(4) @@ -406,9 +409,10 @@ #define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5)) #define SCR_TWEDEL_SHIFT U(30) #define SCR_TWEDEL_MASK ULL(0xf) +#define SCR_AMVOFFEN_BIT (UL(1) << 35) #define SCR_TWEDEn_BIT (UL(1) << 29) -#define SCR_ECVEN_BIT (UL(1) << 28) -#define SCR_FGTEN_BIT (UL(1) << 27) +#define SCR_ECVEN_BIT (UL(1) << 28) +#define SCR_FGTEN_BIT (UL(1) << 27) #define SCR_ATA_BIT (UL(1) << 26) #define SCR_FIEN_BIT (UL(1) << 21) #define SCR_EEL2_BIT (UL(1) << 18) @@ -479,6 +483,7 @@ #define VTTBR_BADDR_SHIFT U(0) /* HCR definitions */ +#define HCR_AMVOFFEN_BIT (ULL(1) << 51) #define HCR_API_BIT (ULL(1) << 41) #define HCR_APK_BIT (ULL(1) << 40) #define HCR_E2H_BIT (ULL(1) << 34) @@ -721,13 +726,13 @@ #define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */ /* Physical timer control register bit fields shifts and masks */ -#define CNTP_CTL_ENABLE_SHIFT U(0) -#define CNTP_CTL_IMASK_SHIFT U(1) -#define CNTP_CTL_ISTATUS_SHIFT U(2) +#define CNTP_CTL_ENABLE_SHIFT U(0) +#define CNTP_CTL_IMASK_SHIFT U(1) +#define CNTP_CTL_ISTATUS_SHIFT U(2) -#define CNTP_CTL_ENABLE_MASK U(1) -#define CNTP_CTL_IMASK_MASK U(1) -#define CNTP_CTL_ISTATUS_MASK U(1) +#define CNTP_CTL_ENABLE_MASK U(1) +#define CNTP_CTL_IMASK_MASK U(1) +#define CNTP_CTL_ISTATUS_MASK U(1) /* Physical timer control macros */ #define CNTP_CTL_ENABLE_BIT (U(1) << CNTP_CTL_ENABLE_SHIFT) @@ -913,7 +918,7 @@ #define MPAM3_EL3 S3_6_C10_C5_0 /******************************************************************************* - * Definitions for system register interface to AMU for ARMv8.4 onwards + * Definitions for system register interface to AMU for FEAT_AMUv1 ******************************************************************************/ #define AMCR_EL0 S3_3_C13_C2_0 #define AMCFGR_EL0 S3_3_C13_C2_1 @@ -992,6 +997,50 @@ #define MPAMIDR_HAS_HCR_BIT (ULL(1) << 17) /******************************************************************************* + * Definitions for system register interface to AMU for FEAT_AMUv1p1 + ******************************************************************************/ + +/* Definition for register defining which virtual offsets are implemented. */ +#define AMCG1IDR_EL0 S3_3_C13_C2_6 +#define AMCG1IDR_CTR_MASK ULL(0xffff) +#define AMCG1IDR_CTR_SHIFT U(0) +#define AMCG1IDR_VOFF_MASK ULL(0xffff) +#define AMCG1IDR_VOFF_SHIFT U(16) + +/* New bit added to AMCR_EL0 */ +#define AMCR_CG1RZ_BIT (ULL(0x1) << 17) + +/* + * Definitions for virtual offset registers for architected activity monitor + * event counters. + * AMEVCNTVOFF01_EL2 intentionally left undefined, as it does not exist. + */ +#define AMEVCNTVOFF00_EL2 S3_4_C13_C8_0 +#define AMEVCNTVOFF02_EL2 S3_4_C13_C8_2 +#define AMEVCNTVOFF03_EL2 S3_4_C13_C8_3 + +/* + * Definitions for virtual offset registers for auxiliary activity monitor event + * counters. + */ +#define AMEVCNTVOFF10_EL2 S3_4_C13_C10_0 +#define AMEVCNTVOFF11_EL2 S3_4_C13_C10_1 +#define AMEVCNTVOFF12_EL2 S3_4_C13_C10_2 +#define AMEVCNTVOFF13_EL2 S3_4_C13_C10_3 +#define AMEVCNTVOFF14_EL2 S3_4_C13_C10_4 +#define AMEVCNTVOFF15_EL2 S3_4_C13_C10_5 +#define AMEVCNTVOFF16_EL2 S3_4_C13_C10_6 +#define AMEVCNTVOFF17_EL2 S3_4_C13_C10_7 +#define AMEVCNTVOFF18_EL2 S3_4_C13_C11_0 +#define AMEVCNTVOFF19_EL2 S3_4_C13_C11_1 +#define AMEVCNTVOFF1A_EL2 S3_4_C13_C11_2 +#define AMEVCNTVOFF1B_EL2 S3_4_C13_C11_3 +#define AMEVCNTVOFF1C_EL2 S3_4_C13_C11_4 +#define AMEVCNTVOFF1D_EL2 S3_4_C13_C11_5 +#define AMEVCNTVOFF1E_EL2 S3_4_C13_C11_6 +#define AMEVCNTVOFF1F_EL2 S3_4_C13_C11_7 + +/******************************************************************************* * RAS system registers ******************************************************************************/ #define DISR_EL1 S3_0_C12_C1_1 diff --git a/include/arch/aarch64/arch_features.h b/include/arch/aarch64/arch_features.h index 671b3dc604..47a797a178 100644 --- a/include/arch/aarch64/arch_features.h +++ b/include/arch/aarch64/arch_features.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2020, Arm Limited. All rights reserved. + * Copyright (c) 2019-2021, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -82,6 +82,12 @@ static inline bool is_armv8_5_rng_present(void) ID_AA64ISAR0_RNDR_MASK); } +static inline bool is_armv8_6_feat_amuv1p1_present(void) +{ + return (((read_id_aa64pfr0_el1() >> ID_AA64PFR0_AMU_SHIFT) & + ID_AA64PFR0_AMU_MASK) >= ID_AA64PFR0_AMU_V1P1); +} + /* * Return MPAM version: * diff --git a/include/arch/aarch64/arch_helpers.h b/include/arch/aarch64/arch_helpers.h index 7fafafc5a0..8c3400a1df 100644 --- a/include/arch/aarch64/arch_helpers.h +++ b/include/arch/aarch64/arch_helpers.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -485,6 +485,8 @@ DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sgi1r, ICC_SGI1R) DEFINE_RENAME_SYSREG_READ_FUNC(amcfgr_el0, AMCFGR_EL0) DEFINE_RENAME_SYSREG_READ_FUNC(amcgcr_el0, AMCGCR_EL0) +DEFINE_RENAME_SYSREG_READ_FUNC(amcg1idr_el0, AMCG1IDR_EL0) +DEFINE_RENAME_SYSREG_RW_FUNCS(amcr_el0, AMCR_EL0) DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenclr0_el0, AMCNTENCLR0_EL0) DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenset0_el0, AMCNTENSET0_EL0) DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenclr1_el0, AMCNTENCLR1_EL0) diff --git a/include/lib/extensions/amu.h b/include/lib/extensions/amu.h index dcbdd5a674..3a70e4ffef 100644 --- a/include/lib/extensions/amu.h +++ b/include/lib/extensions/amu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -66,19 +66,31 @@ CASSERT(AMU_GROUP1_COUNTERS_MASK <= 0xffff, invalid_amu_group1_counters_mask); struct amu_ctx { uint64_t group0_cnts[AMU_GROUP0_NR_COUNTERS]; +#if __aarch64__ + /* Architected event counter 1 does not have an offset register. */ + uint64_t group0_voffsets[AMU_GROUP0_NR_COUNTERS-1]; +#endif #if AMU_GROUP1_NR_COUNTERS uint64_t group1_cnts[AMU_GROUP1_NR_COUNTERS]; +#if __aarch64__ + uint64_t group1_voffsets[AMU_GROUP1_NR_COUNTERS]; +#endif #endif }; -bool amu_supported(void); +unsigned int amu_get_version(void); void amu_enable(bool el2_unused); /* Group 0 configuration helpers */ uint64_t amu_group0_cnt_read(unsigned int idx); void amu_group0_cnt_write(unsigned int idx, uint64_t val); +#if __aarch64__ +uint64_t amu_group0_voffset_read(unsigned int idx); +void amu_group0_voffset_write(unsigned int idx, uint64_t val); +#endif + #if AMU_GROUP1_NR_COUNTERS bool amu_group1_supported(void); @@ -86,6 +98,12 @@ bool amu_group1_supported(void); uint64_t amu_group1_cnt_read(unsigned int idx); void amu_group1_cnt_write(unsigned int idx, uint64_t val); void amu_group1_set_evtype(unsigned int idx, unsigned int val); + +#if __aarch64__ +uint64_t amu_group1_voffset_read(unsigned int idx); +void amu_group1_voffset_write(unsigned int idx, uint64_t val); +#endif + #endif #endif /* AMU_H */ diff --git a/include/lib/extensions/amu_private.h b/include/lib/extensions/amu_private.h index 30ce59d3bb..3b4b47ca3a 100644 --- a/include/lib/extensions/amu_private.h +++ b/include/lib/extensions/amu_private.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -16,4 +16,12 @@ uint64_t amu_group1_cnt_read_internal(unsigned int idx); void amu_group1_cnt_write_internal(unsigned int idx, uint64_t val); void amu_group1_set_evtype_internal(unsigned int idx, unsigned int val); +#if __aarch64__ +uint64_t amu_group0_voffset_read_internal(unsigned int idx); +void amu_group0_voffset_write_internal(unsigned int idx, uint64_t val); + +uint64_t amu_group1_voffset_read_internal(unsigned int idx); +void amu_group1_voffset_write_internal(unsigned int idx, uint64_t val); +#endif + #endif /* AMU_PRIVATE_H */ |