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authorAndre Przywara <andre.przywara@arm.com>2021-05-18 15:51:06 +0100
committerAndre Przywara <andre.przywara@arm.com>2021-09-01 16:14:03 +0100
commit858f40e379684fefc8b52c7b9e60576bc3794a69 (patch)
tree6b0ba23592655241749ed93534cdad8727d85614 /include
parentfeb7081863f454b9e465efc074ca669f7a4c783d (diff)
downloadtrusted-firmware-a-858f40e379684fefc8b52c7b9e60576bc3794a69.tar.gz
feat(gicv3): detect GICv4 feature at runtime
At the moment we have a GIC_ENABLE_V4_EXTN build time variable to determine whether the GIC interrupt controller is compliant to version 4.0 of the spec or not. This just changes the number of 64K MMIO pages we expect per redistributor. To support firmware builds which run on variable systems (emulators, fast model or FPGAs), let's make this decision at runtime. The GIC specification provides several architected flags to learn the size of the MMIO frame per redistributor, we use GICR_TYPER[VLPI] here. Provide a (static inline) function to return the size of each redistributor. We keep the GIC_ENABLE_V4_EXTN build time variable around, but change its meaning to enable this autodetection code. Systems not defining this rely on a "pure" GICv3 (as before), but platforms setting it to "1" can now deal with both configurations. Change-Id: I9ede4acf058846157a0a9e2ef6103bf07c7655d9 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Diffstat (limited to 'include')
-rw-r--r--include/drivers/arm/gicv3.h22
1 files changed, 17 insertions, 5 deletions
diff --git a/include/drivers/arm/gicv3.h b/include/drivers/arm/gicv3.h
index d8ac4cb334..fa8946b168 100644
--- a/include/drivers/arm/gicv3.h
+++ b/include/drivers/arm/gicv3.h
@@ -153,11 +153,8 @@
/*******************************************************************************
* Common GIC Redistributor interface registers & constants
******************************************************************************/
-#if GIC_ENABLE_V4_EXTN
-#define GICR_PCPUBASE_SHIFT 0x12
-#else
-#define GICR_PCPUBASE_SHIFT 0x11
-#endif
+#define GICR_V4_PCPUBASE_SHIFT 0x12
+#define GICR_V3_PCPUBASE_SHIFT 0x11
#define GICR_SGIBASE_OFFSET U(65536) /* 64 KB */
#define GICR_CTLR U(0x0)
#define GICR_IIDR U(0x04)
@@ -212,12 +209,14 @@
#define TYPER_AFF_VAL_SHIFT 32
#define TYPER_PROC_NUM_SHIFT 8
#define TYPER_LAST_SHIFT 4
+#define TYPER_VLPI_SHIFT 1
#define TYPER_AFF_VAL_MASK U(0xffffffff)
#define TYPER_PROC_NUM_MASK U(0xffff)
#define TYPER_LAST_MASK U(0x1)
#define TYPER_LAST_BIT BIT_32(TYPER_LAST_SHIFT)
+#define TYPER_VLPI_BIT BIT_32(TYPER_VLPI_SHIFT)
#define TYPER_PPI_NUM_SHIFT U(27)
#define TYPER_PPI_NUM_MASK U(0x1f)
@@ -312,6 +311,19 @@
#include <drivers/arm/gic_common.h>
#include <lib/utils_def.h>
+static inline uintptr_t gicv3_redist_size(uint64_t typer_val)
+{
+#if GIC_ENABLE_V4_EXTN
+ if ((typer_val & TYPER_VLPI_BIT) != 0U) {
+ return 1U << GICR_V4_PCPUBASE_SHIFT;
+ } else {
+ return 1U << GICR_V3_PCPUBASE_SHIFT;
+ }
+#else
+ return 1U << GICR_V3_PCPUBASE_SHIFT;
+#endif
+}
+
static inline bool gicv3_is_intr_id_special_identifier(unsigned int id)
{
return (id >= PENDING_G1S_INTID) && (id <= GIC_SPURIOUS_INTERRUPT);