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authorManish Pandey <manish.pandey2@arm.com>2021-04-27 11:44:31 +0200
committerTrustedFirmware Code Review <review@review.trustedfirmware.org>2021-04-27 11:44:31 +0200
commit815794220bfa883e99476b7664c338fd2dc897a9 (patch)
treeb834e232d879d6f9e70fc23148fe7ac849845a2e /include
parent303f543e12db6ea0c3722fff8cd6fd09f726d25b (diff)
parentc7d3147466f45a0d8b0d302918b5f3a2337fa086 (diff)
downloadtrusted-firmware-a-815794220bfa883e99476b7664c338fd2dc897a9.tar.gz
Merge changes I36e45c0a,I69c21293 into integration
* changes: plat/qemu: add "max" cpu support Add support for QEMU "max" CPU
Diffstat (limited to 'include')
-rw-r--r--include/lib/cpus/aarch64/qemu_max.h22
1 files changed, 22 insertions, 0 deletions
diff --git a/include/lib/cpus/aarch64/qemu_max.h b/include/lib/cpus/aarch64/qemu_max.h
new file mode 100644
index 0000000000..14da170398
--- /dev/null
+++ b/include/lib/cpus/aarch64/qemu_max.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef QEMU_MAX_H
+#define QEMU_MAX_H
+
+#include <lib/utils_def.h>
+
+/*
+ * QEMU MAX midr for revision 0
+ * 00 - Reserved for software use
+ * 0 - Variant
+ * F - Architectural features identified in ID_* registers
+ * 051 - 'Q', in a 12-bit field.
+ * 0 - Revision
+ */
+#define QEMU_MAX_MIDR U(0x000F0510)
+
+#endif /* QEMU_MAX_H */