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authorManish Pandey <manish.pandey2@arm.com>2020-09-03 21:16:17 +0000
committerTrustedFirmware Code Review <review@review.trustedfirmware.org>2020-09-03 21:16:17 +0000
commit7ef3e0b31baa6a718e0e99d96e65b82c27a08f0b (patch)
tree311da1862e88571d573fa22ed414253aeb8dfaf5 /include
parent86f75c2492d362a13814fbc13cbe43b608b88d7e (diff)
parent942013e1dd57429432cd71cfe121d702e3c52465 (diff)
downloadtrusted-firmware-a-7ef3e0b31baa6a718e0e99d96e65b82c27a08f0b.tar.gz
Merge "lib: cpu: Check SCU presence in DSU before accessing DSU registers" into integration
Diffstat (limited to 'include')
-rw-r--r--include/lib/cpus/aarch64/neoverse_n1.h8
1 files changed, 8 insertions, 0 deletions
diff --git a/include/lib/cpus/aarch64/neoverse_n1.h b/include/lib/cpus/aarch64/neoverse_n1.h
index b50befa8d8..9998b93f29 100644
--- a/include/lib/cpus/aarch64/neoverse_n1.h
+++ b/include/lib/cpus/aarch64/neoverse_n1.h
@@ -64,4 +64,12 @@
#define CPUPOR_EL3 S3_6_C15_C8_2
#define CPUPMR_EL3 S3_6_C15_C8_3
+/******************************************************************************
+ * CPU Configuration register definitions.
+ *****************************************************************************/
+#define CPUCFR_EL1 S3_0_C15_C0_0
+
+/* SCU bit of CPU Configuration Register, EL1 */
+#define SCU_SHIFT U(2)
+
#endif /* NEOVERSE_N1_H */