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authorLin Ma <lin.ma@caviumnetworks.com>2014-06-27 16:56:30 -0700
committerDan Handley <dan.handley@arm.com>2014-07-09 12:33:33 +0100
commit73ad2572c886994e9e0418b2a293570efe90b20c (patch)
tree153c83bc9807bffe3c7455aad4df9ae237469cb9 /include
parentdac1235a94f4633b838598fb40e03e350e89f089 (diff)
downloadtrusted-firmware-a-73ad2572c886994e9e0418b2a293570efe90b20c.tar.gz
Calculate TCR bits based on VA and PA
Currently the TCR bits are hardcoded in xlat_tables.c. In order to map higher physical address into low virtual address, the TCR bits need to be configured accordingly. This patch is to save the max VA and PA and calculate the TCR.PS/IPS and t0sz bits in init_xlat_tables function. Change-Id: Ia7a58e5372b20200153057d457f4be5ddbb7dae4
Diffstat (limited to 'include')
-rw-r--r--include/lib/aarch64/arch.h19
1 files changed, 17 insertions, 2 deletions
diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h
index 5dc488bb1c..ff91efc41a 100644
--- a/include/lib/aarch64/arch.h
+++ b/include/lib/aarch64/arch.h
@@ -211,8 +211,23 @@
* TCR defintions
*/
#define TCR_EL3_RES1 ((1UL << 31) | (1UL << 23))
-
-#define TCR_T0SZ_4GB 32
+#define TCR_EL1_IPS_SHIFT 32
+#define TCR_EL3_PS_SHIFT 16
+
+/* (internal) physical address size bits in EL3/EL1 */
+#define TCR_PS_BITS_4GB (0x0)
+#define TCR_PS_BITS_64GB (0x1)
+#define TCR_PS_BITS_1TB (0x2)
+#define TCR_PS_BITS_4TB (0x3)
+#define TCR_PS_BITS_16TB (0x4)
+#define TCR_PS_BITS_256TB (0x5)
+
+#define ADDR_MASK_48_TO_63 0xFFFF000000000000UL
+#define ADDR_MASK_44_TO_47 0x0000F00000000000UL
+#define ADDR_MASK_42_TO_43 0x00000C0000000000UL
+#define ADDR_MASK_40_TO_41 0x0000030000000000UL
+#define ADDR_MASK_36_TO_39 0x000000F000000000UL
+#define ADDR_MASK_32_TO_35 0x0000000F00000000UL
#define TCR_RGN_INNER_NC (0x0 << 8)
#define TCR_RGN_INNER_WBA (0x1 << 8)