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authorUsama Arif <usama.arif@arm.com>2020-11-18 16:46:32 +0000
committerUsama Arif <usama.arif@arm.com>2021-03-10 16:09:31 +0000
commit614c14e7781ef63f2aaf145549acaf7d5c2e5c30 (patch)
treebd3c562c55a0b22cd5fb78140850e839c2cbf9cb /include
parenta8fb76e59cbd1dd72acaadd4e27b243511d2de2e (diff)
downloadtrusted-firmware-a-614c14e7781ef63f2aaf145549acaf7d5c2e5c30.tar.gz
cpus: add Matterhorn ELP ARM cpu library
Change-Id: Ie1acde619a5b21e09717c0e80befb6d53fd16607 Signed-off-by: Usama Arif <usama.arif@arm.com>
Diffstat (limited to 'include')
-rw-r--r--include/lib/cpus/aarch64/cortex_matterhorn_elp_arm.h23
1 files changed, 23 insertions, 0 deletions
diff --git a/include/lib/cpus/aarch64/cortex_matterhorn_elp_arm.h b/include/lib/cpus/aarch64/cortex_matterhorn_elp_arm.h
new file mode 100644
index 0000000000..309578ecd0
--- /dev/null
+++ b/include/lib/cpus/aarch64/cortex_matterhorn_elp_arm.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2021, ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CORTEX_MATTERHORN_ELP_ARM_H
+#define CORTEX_MATTERHORN_ELP_ARM_H
+
+#define CORTEX_MATTERHORN_ELP_ARM_MIDR U(0x410FD480)
+
+/*******************************************************************************
+ * CPU Extended Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_MATTERHORN_ELP_ARM_CPUECTLR_EL1 S3_0_C15_C1_4
+
+/*******************************************************************************
+ * CPU Power Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_MATTERHORN_ELP_ARM_CPUPWRCTLR_EL1 S3_0_C15_C2_7
+#define CORTEX_MATTERHORN_ELP_ARM_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
+
+#endif /* CORTEX_MATTERHORN_ELP_ARM_H */