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authorManish V Badarkhe <Manish.Badarkhe@arm.com>2021-06-23 20:02:39 +0100
committerManish V Badarkhe <Manish.Badarkhe@arm.com>2021-08-25 18:01:16 +0100
commit40ff90747098ed9d2a09894d1a886c10ca76cee6 (patch)
tree3bbdff926dcaefa762ff621451ca430a389ee60f /include
parentabd63ed0c575a2517c43fe8dc4321d6e9fc512c3 (diff)
downloadtrusted-firmware-a-40ff90747098ed9d2a09894d1a886c10ca76cee6.tar.gz
feat(trbe): initialize trap settings of trace buffer control registers access
Trap bits of trace buffer control registers access are in architecturally UNKNOWN state at boot hence 1. Initialized these bits to zero to prohibit trace buffer control registers accesses in lower ELs (EL2, EL1) in all security states when FEAT_TRBE is implemented 2. Also, these bits are RES0 when FEAT_TRBE is not implemented, and hence setting it to zero also aligns with the Arm ARM reference recommendation, that mentions software must writes RES0 bits with all 0s Change-Id: If2752fd314881219f232f21d8e172a9c6d341ea1 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Diffstat (limited to 'include')
-rw-r--r--include/arch/aarch64/arch.h5
-rw-r--r--include/arch/aarch64/el3_common_macros.S9
2 files changed, 13 insertions, 1 deletions
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index c12dbc4b4d..d71ec00c99 100644
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h
@@ -442,6 +442,9 @@
#define MDCR_EnPMSN_BIT (ULL(1) << 36)
#define MDCR_MPMX_BIT (ULL(1) << 35)
#define MDCR_MCCD_BIT (ULL(1) << 34)
+#define MDCR_NSTB(x) ((x) << 24)
+#define MDCR_NSTB_EL1 ULL(0x3)
+#define MDCR_NSTBE (ULL(1) << 26)
#define MDCR_MTPME_BIT (ULL(1) << 28)
#define MDCR_TDCC_BIT (ULL(1) << 27)
#define MDCR_SCCD_BIT (ULL(1) << 23)
@@ -465,6 +468,8 @@
/* MDCR_EL2 definitions */
#define MDCR_EL2_MTPME (U(1) << 28)
#define MDCR_EL2_HLP (U(1) << 26)
+#define MDCR_EL2_E2TB(x) ((x) << 24)
+#define MDCR_EL2_E2TB_EL1 U(0x3)
#define MDCR_EL2_HCCD (U(1) << 23)
#define MDCR_EL2_TTRF (U(1) << 19)
#define MDCR_EL2_HPMD (U(1) << 17)
diff --git a/include/arch/aarch64/el3_common_macros.S b/include/arch/aarch64/el3_common_macros.S
index 9734335755..2aa22226f5 100644
--- a/include/arch/aarch64/el3_common_macros.S
+++ b/include/arch/aarch64/el3_common_macros.S
@@ -126,12 +126,19 @@
* Debug is not implemented this bit does not have any effect on the
* counters unless there is support for the implementation defined
* authentication interface ExternalSecureNoninvasiveDebugEnabled().
+ *
+ * MDCR_EL3.NSTB, MDCR_EL3.NSTBE: Set to zero so that Trace Buffer
+ * owning security state is Secure state. If FEAT_TRBE is implemented,
+ * accesses to Trace Buffer control registers at EL2 and EL1 in any
+ * security state generates trap exceptions to EL3.
+ * If FEAT_TRBE is not implemented, these bits are RES0.
* ---------------------------------------------------------------------
*/
mov_imm x0, ((MDCR_EL3_RESET_VAL | MDCR_SDD_BIT | \
MDCR_SPD32(MDCR_SPD32_DISABLE) | MDCR_SCCD_BIT | \
MDCR_MCCD_BIT) & ~(MDCR_SPME_BIT | MDCR_TDOSA_BIT | \
- MDCR_TDA_BIT | MDCR_TPM_BIT))
+ MDCR_TDA_BIT | MDCR_TPM_BIT | MDCR_NSTB(MDCR_NSTB_EL1) | \
+ MDCR_NSTBE))
msr mdcr_el3, x0