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authorHeyi Guo <guoheyi@linux.alibaba.com>2020-05-13 16:25:37 +0800
committerHeyi Guo <guoheyi@linux.alibaba.com>2021-02-09 10:41:58 +0800
commit3d66ca6d8cf35f198d637f8fda233601fcfb04d7 (patch)
tree0ca0281115a27ae1e8008e1fd75f78b9ff2e928f /include
parent9192f34e65bca113a7d662a92deebdb6267ad35a (diff)
downloadtrusted-firmware-a-3d66ca6d8cf35f198d637f8fda233601fcfb04d7.tar.gz
tzc400: fix logical error in FILTER_BIT definitions
The filters parameter passed to tzc400_configure_region() is supposed to be filter bit flag without bit shift, so the macros TZC_400_REGION_ATTR_FILTER_BIT and TZC_400_REGION_ATTR_FILTER_BIT_ALL should always construct the value without any shift. It is not a functional issue for TZC_REGION_ATTR_F_EN_SHIFT is lucky to be 0. Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com> Change-Id: I5d363c462b8517256523f637e670eefa56722afd
Diffstat (limited to 'include')
-rw-r--r--include/drivers/arm/tzc400.h9
1 files changed, 3 insertions, 6 deletions
diff --git a/include/drivers/arm/tzc400.h b/include/drivers/arm/tzc400.h
index 32aeb03502..cf2e82bc55 100644
--- a/include/drivers/arm/tzc400.h
+++ b/include/drivers/arm/tzc400.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -80,11 +80,8 @@
/* Filter enable bits in a TZC */
#define TZC_400_REGION_ATTR_F_EN_MASK U(0xf)
-#define TZC_400_REGION_ATTR_FILTER_BIT(x) \
- ((U(1) << (x)) << TZC_REGION_ATTR_F_EN_SHIFT)
-#define TZC_400_REGION_ATTR_FILTER_BIT_ALL \
- (TZC_400_REGION_ATTR_F_EN_MASK << \
- TZC_REGION_ATTR_F_EN_SHIFT)
+#define TZC_400_REGION_ATTR_FILTER_BIT(x) (U(1) << (x))
+#define TZC_400_REGION_ATTR_FILTER_BIT_ALL TZC_400_REGION_ATTR_F_EN_MASK
/*
* All TZC region configuration registers are placed one after another. It