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author | johpow01 <john.powell@arm.com> | 2020-10-07 15:08:01 -0500 |
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committer | johpow01 <john.powell@arm.com> | 2021-01-13 13:54:18 -0600 |
commit | 3a2710dcab0dc6dc625f0a4956a44bace1788618 (patch) | |
tree | c027995bd640eda1c72607dd5c2e468164b9a6d2 /include | |
parent | e26c59d2c968eb0122bf1c333d5ceba534d5fe45 (diff) | |
download | trusted-firmware-a-3a2710dcab0dc6dc625f0a4956a44bace1788618.tar.gz |
Workaround for Cortex A78 erratum 1951500
Cortex A78 erratum 1951500 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r1p1. The workaround is to insert a DMB ST before
acquire atomic instructions without release semantics. This workaround
works on revisions r1p0 and r1p1, in r0p0 there is no workaround.
SDEN can be found here:
https://documentation-service.arm.com/static/5fb66157ca04df4095c1cc2e
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I47610cee75af6a127ea65edc4d5cffc7e6a2d0a3
Diffstat (limited to 'include')
-rw-r--r-- | include/lib/cpus/errata_report.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/lib/cpus/errata_report.h b/include/lib/cpus/errata_report.h index 7cac77ebe6..efdedf0aaa 100644 --- a/include/lib/cpus/errata_report.h +++ b/include/lib/cpus/errata_report.h @@ -30,4 +30,7 @@ int errata_needs_reporting(spinlock_t *lock, uint32_t *reported); #define ERRATA_APPLIES 1 #define ERRATA_MISSING 2 +/* Macro to get CPU revision code for checking errata version compatibility. */ +#define CPU_REV(r, p) ((r << 4) | p) + #endif /* ERRATA_REPORT_H */ |