diff options
author | Madhukar Pappireddy <madhukar.pappireddy@arm.com> | 2021-05-28 22:08:24 +0200 |
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committer | TrustedFirmware Code Review <review@review.trustedfirmware.org> | 2021-05-28 22:08:24 +0200 |
commit | 2ea8d41979fe1ccf936b079b2271d588511b1c4a (patch) | |
tree | 91b8dc62e2c55cf3bf345ffa2104a70d7389bba5 /include | |
parent | 0f7d2e89111a5bd06735bc4a41893aed3129ace7 (diff) | |
parent | c6ac4df622befb5bb42ac136745094e1498c91d8 (diff) | |
download | trusted-firmware-a-2ea8d41979fe1ccf936b079b2271d588511b1c4a.tar.gz |
Merge "fix: rename Matterhorn, Matterhorn ELP, and Klein CPUs" into integration
Diffstat (limited to 'include')
-rw-r--r-- | include/lib/cpus/aarch64/cortex_a510.h (renamed from include/lib/cpus/aarch64/cortex_matterhorn_elp_arm.h) | 14 | ||||
-rw-r--r-- | include/lib/cpus/aarch64/cortex_a710.h (renamed from include/lib/cpus/aarch64/cortex_klein.h) | 16 | ||||
-rw-r--r-- | include/lib/cpus/aarch64/cortex_x2.h (renamed from include/lib/cpus/aarch64/cortex_matterhorn.h) | 16 |
3 files changed, 23 insertions, 23 deletions
diff --git a/include/lib/cpus/aarch64/cortex_matterhorn_elp_arm.h b/include/lib/cpus/aarch64/cortex_a510.h index 309578ecd0..6a4cfdfe33 100644 --- a/include/lib/cpus/aarch64/cortex_matterhorn_elp_arm.h +++ b/include/lib/cpus/aarch64/cortex_a510.h @@ -4,20 +4,20 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef CORTEX_MATTERHORN_ELP_ARM_H -#define CORTEX_MATTERHORN_ELP_ARM_H +#ifndef CORTEX_A510_H +#define CORTEX_A510_H -#define CORTEX_MATTERHORN_ELP_ARM_MIDR U(0x410FD480) +#define CORTEX_A510_MIDR U(0x410FD460) /******************************************************************************* * CPU Extended Control register specific definitions ******************************************************************************/ -#define CORTEX_MATTERHORN_ELP_ARM_CPUECTLR_EL1 S3_0_C15_C1_4 +#define CORTEX_A510_CPUECTLR_EL1 S3_0_C15_C1_4 /******************************************************************************* * CPU Power Control register specific definitions ******************************************************************************/ -#define CORTEX_MATTERHORN_ELP_ARM_CPUPWRCTLR_EL1 S3_0_C15_C2_7 -#define CORTEX_MATTERHORN_ELP_ARM_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) +#define CORTEX_A510_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_A510_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) -#endif /* CORTEX_MATTERHORN_ELP_ARM_H */ +#endif /* CORTEX_A510_H */ diff --git a/include/lib/cpus/aarch64/cortex_klein.h b/include/lib/cpus/aarch64/cortex_a710.h index 729b3bf0a9..44c540c72d 100644 --- a/include/lib/cpus/aarch64/cortex_klein.h +++ b/include/lib/cpus/aarch64/cortex_a710.h @@ -1,23 +1,23 @@ /* - * Copyright (c) 2020, ARM Limited. All rights reserved. + * Copyright (c) 2021, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef CORTEX_KLEIN_H -#define CORTEX_KLEIN_H +#ifndef CORTEX_A710_H +#define CORTEX_A710_H -#define CORTEX_KLEIN_MIDR U(0x410FD460) +#define CORTEX_A710_MIDR U(0x410FD470) /******************************************************************************* * CPU Extended Control register specific definitions ******************************************************************************/ -#define CORTEX_KLEIN_CPUECTLR_EL1 S3_0_C15_C1_4 +#define CORTEX_A710_CPUECTLR_EL1 S3_0_C15_C1_4 /******************************************************************************* * CPU Power Control register specific definitions ******************************************************************************/ -#define CORTEX_KLEIN_CPUPWRCTLR_EL1 S3_0_C15_C2_7 -#define CORTEX_KLEIN_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) +#define CORTEX_A710_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_A710_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) -#endif /* CORTEX_KLEIN_H */ +#endif /* CORTEX_A710_H */ diff --git a/include/lib/cpus/aarch64/cortex_matterhorn.h b/include/lib/cpus/aarch64/cortex_x2.h index 018553359b..9ce1223c8b 100644 --- a/include/lib/cpus/aarch64/cortex_matterhorn.h +++ b/include/lib/cpus/aarch64/cortex_x2.h @@ -1,23 +1,23 @@ /* - * Copyright (c) 2020, ARM Limited. All rights reserved. + * Copyright (c) 2021, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef CORTEX_MATTERHORN_H -#define CORTEX_MATTERHORN_H +#ifndef CORTEX_X2_H +#define CORTEX_X2_H -#define CORTEX_MATTERHORN_MIDR U(0x410FD470) +#define CORTEX_X2_MIDR U(0x410FD480) /******************************************************************************* * CPU Extended Control register specific definitions ******************************************************************************/ -#define CORTEX_MATTERHORN_CPUECTLR_EL1 S3_0_C15_C1_4 +#define CORTEX_X2_CPUECTLR_EL1 S3_0_C15_C1_4 /******************************************************************************* * CPU Power Control register specific definitions ******************************************************************************/ -#define CORTEX_MATTERHORN_CPUPWRCTLR_EL1 S3_0_C15_C2_7 -#define CORTEX_MATTERHORN_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) +#define CORTEX_X2_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) -#endif /* CORTEX_MATTERHORN_H */ +#endif /* CORTEX_X2_H */ |