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authorManish Pandey <manish.pandey2@arm.com>2021-06-16 12:03:17 +0200
committerTrustedFirmware Code Review <review@review.trustedfirmware.org>2021-06-16 12:03:17 +0200
commit2a0087796f84a462280ded3cde83635022ae9ef5 (patch)
treed846d627aab8219cbe66549797322b6ef7088d69 /include
parented0f0a096845d8b0c0ee9db7a2d6a6486e3ddb44 (diff)
parent46b90333593cd1a6da56eabe711753242f66fde0 (diff)
downloadtrusted-firmware-a-2a0087796f84a462280ded3cde83635022ae9ef5.tar.gz
Merge changes from topic "soc_id" into integration
* changes: refactor(plat/nvidia): use SOC_ID defines refactor(plat/mediatek): use SOC_ID defines refactor(plat/arm): use SOC_ID defines feat(plat/st): implement platform functions for SMCCC_ARCH_SOC_ID refactor(plat/st): export functions to get SoC information feat(smccc): add bit definition for SMCCC_ARCH_SOC_ID
Diffstat (limited to 'include')
-rw-r--r--include/lib/smccc.h19
-rw-r--r--include/plat/arm/common/smccc_def.h4
2 files changed, 19 insertions, 4 deletions
diff --git a/include/lib/smccc.h b/include/lib/smccc.h
index 470317dd00..deaeb1d1d1 100644
--- a/include/lib/smccc.h
+++ b/include/lib/smccc.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -51,6 +51,23 @@
FUNCID_OEN_MASK)
/*******************************************************************************
+ * SMCCC_ARCH_SOC_ID SoC version & revision bit definition
+ ******************************************************************************/
+#define SOC_ID_JEP_106_BANK_IDX_MASK GENMASK_32(30, 24)
+#define SOC_ID_JEP_106_BANK_IDX_SHIFT U(24)
+#define SOC_ID_JEP_106_ID_CODE_MASK GENMASK_32(23, 16)
+#define SOC_ID_JEP_106_ID_CODE_SHIFT U(16)
+#define SOC_ID_IMPL_DEF_MASK GENMASK_32(15, 0)
+#define SOC_ID_IMPL_DEF_SHIFT U(0)
+#define SOC_ID_SET_JEP_106(bkid, mfid) ((((bkid) << SOC_ID_JEP_106_BANK_IDX_SHIFT) & \
+ SOC_ID_JEP_106_BANK_IDX_MASK) | \
+ (((mfid) << SOC_ID_JEP_106_ID_CODE_SHIFT) & \
+ SOC_ID_JEP_106_ID_CODE_MASK))
+
+#define SOC_ID_REV_MASK GENMASK_32(30, 0)
+#define SOC_ID_REV_SHIFT U(0)
+
+/*******************************************************************************
* Owning entity number definitions inside the function id as per the SMC
* calling convention
******************************************************************************/
diff --git a/include/plat/arm/common/smccc_def.h b/include/plat/arm/common/smccc_def.h
index 6e698e5d2c..0f4e57386f 100644
--- a/include/plat/arm/common/smccc_def.h
+++ b/include/plat/arm/common/smccc_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,7 +9,5 @@
/* Defines used to retrieve ARM SOC revision */
#define ARM_SOC_CONTINUATION_CODE U(0x4)
#define ARM_SOC_IDENTIFICATION_CODE U(0x3B)
-#define ARM_SOC_CONTINUATION_SHIFT U(24)
-#define ARM_SOC_IDENTIFICATION_SHIFT U(16)
#endif /* SMCCC_DEF_H */