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authorSandrine Bailleux <sandrine.bailleux@arm.com>2021-01-26 14:58:00 +0000
committerTrustedFirmware Code Review <review@review.trustedfirmware.org>2021-01-26 14:58:00 +0000
commit1ddf38e853cd7cb3fa02678f310ee8aa4f13bb22 (patch)
treee1a96388bc99bb5f46236439b7dcbdeaeb2f9b3b /include
parent036e9c177f8ac4ece205607fba98b0a16dc45703 (diff)
parent83683ddd3d704e2d8c1fe9bef9eabb4639c0846a (diff)
downloadtrusted-firmware-a-1ddf38e853cd7cb3fa02678f310ee8aa4f13bb22.tar.gz
Merge changes from topic "tp-feat-rng" into integration
* changes: plat/qemu: Use RNDR in stack protector Makefile: Add FEAT_RNG support define Define registers for FEAT_RNG support
Diffstat (limited to 'include')
-rw-r--r--include/arch/aarch64/arch.h4
-rw-r--r--include/arch/aarch64/arch_features.h6
-rw-r--r--include/arch/aarch64/arch_helpers.h5
3 files changed, 15 insertions, 0 deletions
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index 09e598a2db..2cdc7b2303 100644
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h
@@ -193,6 +193,10 @@
#define ID_AA64DFR0_MTPMU_MASK ULL(0xf)
#define ID_AA64DFR0_MTPMU_SUPPORTED ULL(1)
+/* ID_AA64ISAR0_EL1 definitions */
+#define ID_AA64ISAR0_RNDR_SHIFT U(60)
+#define ID_AA64ISAR0_RNDR_MASK ULL(0xf)
+
/* ID_AA64ISAR1_EL1 definitions */
#define ID_AA64ISAR1_EL1 S3_0_C0_C6_1
#define ID_AA64ISAR1_GPI_SHIFT U(28)
diff --git a/include/arch/aarch64/arch_features.h b/include/arch/aarch64/arch_features.h
index 6b5d326960..671b3dc604 100644
--- a/include/arch/aarch64/arch_features.h
+++ b/include/arch/aarch64/arch_features.h
@@ -76,6 +76,12 @@ static inline unsigned long int get_armv8_6_ecv_support(void)
ID_AA64MMFR0_EL1_ECV_MASK);
}
+static inline bool is_armv8_5_rng_present(void)
+{
+ return ((read_id_aa64isar0_el1() >> ID_AA64ISAR0_RNDR_SHIFT) &
+ ID_AA64ISAR0_RNDR_MASK);
+}
+
/*
* Return MPAM version:
*
diff --git a/include/arch/aarch64/arch_helpers.h b/include/arch/aarch64/arch_helpers.h
index 5d1bc948c8..7fafafc5a0 100644
--- a/include/arch/aarch64/arch_helpers.h
+++ b/include/arch/aarch64/arch_helpers.h
@@ -245,6 +245,7 @@ void disable_mmu_icache_el3(void);
DEFINE_SYSREG_RW_FUNCS(par_el1)
DEFINE_SYSREG_READ_FUNC(id_pfr1_el1)
+DEFINE_SYSREG_READ_FUNC(id_aa64isar0_el1)
DEFINE_SYSREG_READ_FUNC(id_aa64isar1_el1)
DEFINE_SYSREG_READ_FUNC(id_aa64pfr0_el1)
DEFINE_SYSREG_READ_FUNC(id_aa64pfr1_el1)
@@ -522,6 +523,10 @@ DEFINE_RENAME_SYSREG_RW_FUNCS(tfsr_el1, TFSR_EL1)
DEFINE_RENAME_SYSREG_RW_FUNCS(rgsr_el1, RGSR_EL1)
DEFINE_RENAME_SYSREG_RW_FUNCS(gcr_el1, GCR_EL1)
+/* Armv8.5 FEAT_RNG Registers */
+DEFINE_SYSREG_READ_FUNC(rndr)
+DEFINE_SYSREG_READ_FUNC(rndrrs)
+
/* DynamIQ Shared Unit power management */
DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpwrdn_el1, CLUSTERPWRDN_EL1)