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authorManish Pandey <manish.pandey2@arm.com>2021-04-29 13:57:31 +0200
committerTrustedFirmware Code Review <review@review.trustedfirmware.org>2021-04-29 13:57:31 +0200
commit08e7cc533e5a019b53e466a3e03eb646980710fa (patch)
treec492c08b08291e0701c92e9b1aef3119e8003490 /include
parent800b8849c0e2ca0ac2eaa652d7bd0ed44d36c669 (diff)
parent62fbb31516807207d58cdba705d2adf54fec3a5d (diff)
downloadtrusted-firmware-a-08e7cc533e5a019b53e466a3e03eb646980710fa.tar.gz
Merge changes I15e7cc43,Id7411bd5,I92bafe70,I8f1c0658 into integration
* changes: stm32mp1: enable PIE for BL32 stm32mp1: set BL sizes regardless of flags Add PIE support for AARCH32 Avoid the use of linker *_SIZE__ macros
Diffstat (limited to 'include')
-rw-r--r--include/arch/aarch32/el3_common_macros.S44
-rw-r--r--include/common/bl_common.ld.h14
2 files changed, 50 insertions, 8 deletions
diff --git a/include/arch/aarch32/el3_common_macros.S b/include/arch/aarch32/el3_common_macros.S
index 580dd95b73..7fff4c754e 100644
--- a/include/arch/aarch32/el3_common_macros.S
+++ b/include/arch/aarch32/el3_common_macros.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -10,6 +10,9 @@
#include <arch.h>
#include <asm_macros.S>
#include <assert_macros.S>
+#include <lib/xlat_tables/xlat_tables_defs.h>
+
+#define PAGE_START_MASK ~(PAGE_SIZE_MASK)
/*
* Helper macro to initialise EL3 registers we care about.
@@ -199,11 +202,18 @@
*
* _exception_vectors:
* Address of the exception vectors to program in the VBAR_EL3 register.
+ *
+ * _pie_fixup_size:
+ * Size of memory region to fixup Global Descriptor Table (GDT).
+ *
+ * A non-zero value is expected when firmware needs GDT to be fixed-up.
+ *
* -----------------------------------------------------------------------------
*/
.macro el3_entrypoint_common \
_init_sctlr, _warm_boot_mailbox, _secondary_cold_boot, \
- _init_memory, _init_c_runtime, _exception_vectors
+ _init_memory, _init_c_runtime, _exception_vectors, \
+ _pie_fixup_size
/* Make sure we are in Secure Mode */
#if ENABLE_ASSERTIONS
@@ -259,6 +269,27 @@
bxne r0
.endif /* _warm_boot_mailbox */
+ .if \_pie_fixup_size
+#if ENABLE_PIE
+ /*
+ * ------------------------------------------------------------
+ * If PIE is enabled fixup the Global descriptor Table only
+ * once during primary core cold boot path.
+ *
+ * Compile time base address, required for fixup, is calculated
+ * using "pie_fixup" label present within first page.
+ * ------------------------------------------------------------
+ */
+ pie_fixup:
+ ldr r0, =pie_fixup
+ ldr r1, =PAGE_START_MASK
+ and r0, r0, r1
+ mov_imm r1, \_pie_fixup_size
+ add r1, r1, r0
+ bl fixup_gdt_reloc
+#endif /* ENABLE_PIE */
+ .endif /* _pie_fixup_size */
+
/* ---------------------------------------------------------------------
* Set the exception vectors (VBAR/MVBAR).
* ---------------------------------------------------------------------
@@ -339,12 +370,14 @@
*/
mov r7, r12
ldr r0, =__BSS_START__
- ldr r1, =__BSS_SIZE__
+ ldr r1, =__BSS_END__
+ sub r1, r1, r0
bl zeromem
#if USE_COHERENT_MEM
ldr r0, =__COHERENT_RAM_START__
- ldr r1, =__COHERENT_RAM_UNALIGNED_SIZE__
+ ldr r1, =__COHERENT_RAM_END_UNALIGNED__
+ sub r1, r1, r0
bl zeromem
#endif
@@ -358,7 +391,8 @@
*/
ldr r0, =__DATA_RAM_START__
ldr r1, =__DATA_ROM_START__
- ldr r2, =__DATA_SIZE__
+ ldr r2, =__DATA_RAM_END__
+ sub r2, r2, r0
bl memcpy4
#endif
.endif /* _init_c_runtime */
diff --git a/include/common/bl_common.ld.h b/include/common/bl_common.ld.h
index ab3391aa21..5147e37650 100644
--- a/include/common/bl_common.ld.h
+++ b/include/common/bl_common.ld.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -105,10 +105,18 @@
* .rela.dyn needs to come after .data for the read-elf utility to parse
* this section correctly.
*/
+#if __aarch64__
+#define RELA_DYN_NAME .rela.dyn
+#define RELOC_SECTIONS_PATTERN *(.rela*)
+#else
+#define RELA_DYN_NAME .rel.dyn
+#define RELOC_SECTIONS_PATTERN *(.rel*)
+#endif
+
#define RELA_SECTION \
- .rela.dyn : ALIGN(STRUCT_ALIGN) { \
+ RELA_DYN_NAME : ALIGN(STRUCT_ALIGN) { \
__RELA_START__ = .; \
- *(.rela*) \
+ RELOC_SECTIONS_PATTERN \
__RELA_END__ = .; \
}