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author | Manish V Badarkhe <Manish.Badarkhe@arm.com> | 2020-05-31 10:17:59 +0100 |
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committer | Manish V Badarkhe <Manish.Badarkhe@arm.com> | 2020-06-24 08:44:26 +0100 |
commit | 04e06973e1fef87849c498c7f045aa2be8aada1c (patch) | |
tree | 24d833cffd92b8348f039c3af47995fcfa476301 /include/plat | |
parent | 243875eaf9df591aec14c20075c70cb5af7dd9e9 (diff) | |
download | trusted-firmware-a-04e06973e1fef87849c498c7f045aa2be8aada1c.tar.gz |
fconf: Clean confused naming between TB_FW and FW_CONFIG
Cleaned up confused naming between TB_FW and FW_CONFIG.
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I9e9f6e6ca076d38fee0388f97d370431ae067f08
Diffstat (limited to 'include/plat')
-rw-r--r-- | include/plat/arm/common/arm_def.h | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h index 89f7c61466..a6b6b2eab7 100644 --- a/include/plat/arm/common/arm_def.h +++ b/include/plat/arm/common/arm_def.h @@ -346,24 +346,24 @@ #define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT) /* - * To enable TB_FW_CONFIG to be loaded by BL1, define the corresponding base + * To enable FW_CONFIG to be loaded by BL1, define the corresponding base * and limit. Leave enough space of BL2 meminfo. */ -#define ARM_TB_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t)) -#define ARM_TB_FW_CONFIG_LIMIT (ARM_BL_RAM_BASE + (PAGE_SIZE / 2U)) +#define ARM_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t)) +#define ARM_FW_CONFIG_LIMIT (ARM_BL_RAM_BASE + (PAGE_SIZE / 2U)) /* * Boot parameters passed from BL2 to BL31/BL32 are stored here */ -#define ARM_BL2_MEM_DESC_BASE ARM_TB_FW_CONFIG_LIMIT +#define ARM_BL2_MEM_DESC_BASE ARM_FW_CONFIG_LIMIT #define ARM_BL2_MEM_DESC_LIMIT (ARM_BL2_MEM_DESC_BASE + \ (PAGE_SIZE / 2U)) /* * Define limit of firmware configuration memory: - * ARM_TB_FW_CONFIG + ARM_BL2_MEM_DESC memory + * ARM_FW_CONFIG + ARM_BL2_MEM_DESC memory */ -#define ARM_FW_CONFIG_LIMIT (ARM_BL_RAM_BASE + PAGE_SIZE) +#define ARM_FW_CONFIGS_LIMIT (ARM_BL_RAM_BASE + PAGE_SIZE) /******************************************************************************* * BL1 specific defines. @@ -461,7 +461,7 @@ * SP_MIN is the only BL image in SRAM. Allocate the whole of SRAM (excluding * the page reserved for fw_configs) to BL32 */ -# define BL32_BASE ARM_FW_CONFIG_LIMIT +# define BL32_BASE ARM_FW_CONFIGS_LIMIT # define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) # else /* Put BL32 below BL2 in the Trusted SRAM.*/ @@ -505,7 +505,7 @@ # define TSP_SEC_MEM_BASE ARM_BL_RAM_BASE # define TSP_SEC_MEM_SIZE ARM_BL_RAM_SIZE # define TSP_PROGBITS_LIMIT BL31_BASE -# define BL32_BASE ARM_FW_CONFIG_LIMIT +# define BL32_BASE ARM_FW_CONFIGS_LIMIT # define BL32_LIMIT BL31_BASE # elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_DRAM_ID # define TSP_SEC_MEM_BASE PLAT_ARM_TRUSTED_DRAM_BASE |