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authorYann Gautier <yann.gautier@st.com>2021-02-01 11:14:06 +0100
committerYann Gautier <yann.gautier@foss.st.com>2021-02-04 14:17:32 +0100
commitedaaa98fc5461b01d50d04b4735b42f4413348ca (patch)
tree3a3a8fdbef2a6c8fbf60bd161acb5ce980bfed55 /include/drivers
parentd5105d994c683194dc0310c81624a6837ebda14a (diff)
downloadtrusted-firmware-a-edaaa98fc5461b01d50d04b4735b42f4413348ca.tar.gz
ddr: stm32mp1_ddr: correct SELFREF_TO_X32 mask
In DDR controller PWRTMG register, the mask for field SELFREF_TO_X32 is wrong. This field is from bit 16 to 23. Change-Id: Id336fb08c88f0a153df186dd819e41af72febb88 Signed-off-by: Yann Gautier <yann.gautier@st.com>
Diffstat (limited to 'include/drivers')
-rw-r--r--include/drivers/st/stm32mp1_ddr_regs.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/include/drivers/st/stm32mp1_ddr_regs.h b/include/drivers/st/stm32mp1_ddr_regs.h
index 342239a52d..01d6638348 100644
--- a/include/drivers/st/stm32mp1_ddr_regs.h
+++ b/include/drivers/st/stm32mp1_ddr_regs.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2017-2021, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
*/
@@ -284,7 +284,7 @@ struct stm32mp1_ddrphy {
#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE BIT(3)
#define DDRCTRL_PWRCTL_SELFREF_SW BIT(5)
-#define DDRCTRL_PWRTMG_SELFREF_TO_X32_MASK GENMASK(19, 12)
+#define DDRCTRL_PWRTMG_SELFREF_TO_X32_MASK GENMASK(23, 16)
#define DDRCTRL_PWRTMG_SELFREF_TO_X32_0 BIT(16)
#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH BIT(0)