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authorSheetal Tigadoli <sheetal.tigadoli@broadcom.com>2020-01-05 14:59:04 +0530
committerSheetal Tigadoli <sheetal.tigadoli@broadcom.com>2020-04-03 17:12:42 +0530
commitbffde63de7a2c1a8534c1d969857d17fa17e30df (patch)
tree97d0d7c66e9f36e728510767bfbb295b312732b6 /include/drivers
parent3942d3a8ea0c1deda44e0bb481876f03b256e25d (diff)
downloadtrusted-firmware-a-bffde63de7a2c1a8534c1d969857d17fa17e30df.tar.gz
drivers: Add emmc driver for Broadcom platforms
Add emmc driver for Broadcom platforms Change-Id: I126a6dfccd41062cb0b856f2c2fb1f724730b95e Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com>
Diffstat (limited to 'include/drivers')
-rw-r--r--include/drivers/brcm/emmc/bcm_emmc.h104
-rw-r--r--include/drivers/brcm/emmc/emmc_api.h47
-rw-r--r--include/drivers/brcm/emmc/emmc_brcm_rdb_sd4_top.h1116
-rw-r--r--include/drivers/brcm/emmc/emmc_chal_sd.h202
-rw-r--r--include/drivers/brcm/emmc/emmc_chal_types.h20
-rw-r--r--include/drivers/brcm/emmc/emmc_csl_sd.h96
-rw-r--r--include/drivers/brcm/emmc/emmc_csl_sdcmd.h168
-rw-r--r--include/drivers/brcm/emmc/emmc_csl_sdprot.h435
-rw-r--r--include/drivers/brcm/emmc/emmc_pboot_hal_memory_drv.h94
9 files changed, 2282 insertions, 0 deletions
diff --git a/include/drivers/brcm/emmc/bcm_emmc.h b/include/drivers/brcm/emmc/bcm_emmc.h
new file mode 100644
index 0000000000..67f0602296
--- /dev/null
+++ b/include/drivers/brcm/emmc/bcm_emmc.h
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2016 - 2020, Broadcom
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef EMMC_H
+#define EMMC_H
+
+#include <stdint.h>
+
+#include <common/debug.h>
+
+#include <platform_def.h>
+
+#include "emmc_chal_types.h"
+#include "emmc_chal_sd.h"
+#include "emmc_csl_sdprot.h"
+#include "emmc_csl_sdcmd.h"
+#include "emmc_pboot_hal_memory_drv.h"
+
+/* ------------------------------------------------------------------- */
+#define EXT_CSD_SIZE 512
+
+#ifdef PLAT_SD_MAX_READ_LENGTH
+#define SD_MAX_READ_LENGTH PLAT_SD_MAX_READ_LENGTH
+#ifdef USE_EMMC_LARGE_BLK_TRANSFER_LENGTH
+#define SD_MAX_BLK_TRANSFER_LENGTH 0x10000000
+#else
+#define SD_MAX_BLK_TRANSFER_LENGTH 0x1000
+#endif
+#else
+#define SD_MAX_READ_LENGTH EMMC_BLOCK_SIZE
+#define SD_MAX_BLK_TRANSFER_LENGTH EMMC_BLOCK_SIZE
+#endif
+
+struct emmc_global_buffer {
+ union {
+ uint8_t Ext_CSD_storage[EXT_CSD_SIZE];
+ uint8_t tempbuf[SD_MAX_READ_LENGTH];
+ } u;
+};
+
+struct emmc_global_vars {
+ struct sd_card_data cardData;
+ struct sd_handle sdHandle;
+ struct sd_dev sdDevice;
+ struct sd_card_info sdCard;
+ unsigned int init_done;
+};
+
+#define ICFG_SDIO0_CAP0__SLOT_TYPE_R 27
+#define ICFG_SDIO0_CAP0__INT_MODE_R 26
+#define ICFG_SDIO0_CAP0__SYS_BUS_64BIT_R 25
+#define ICFG_SDIO0_CAP0__VOLTAGE_1P8V_R 24
+#define ICFG_SDIO0_CAP0__VOLTAGE_3P0V_R 23
+#define ICFG_SDIO0_CAP0__VOLTAGE_3P3V_R 22
+#define ICFG_SDIO0_CAP0__SUSPEND_RESUME_R 21
+#define ICFG_SDIO0_CAP0__SDMA_R 20
+#define ICFG_SDIO0_CAP0__HIGH_SPEED_R 19
+#define ICFG_SDIO0_CAP0__ADMA2_R 18
+#define ICFG_SDIO0_CAP0__EXTENDED_MEDIA_R 17
+#define ICFG_SDIO0_CAP0__MAX_BLOCK_LEN_R 15
+#define ICFG_SDIO0_CAP0__BASE_CLK_FREQ_R 7
+#define ICFG_SDIO0_CAP0__TIMEOUT_UNIT_R 6
+#define ICFG_SDIO0_CAP0__TIMEOUT_CLK_FREQ_R 0
+#define ICFG_SDIO0_CAP1__SPI_BLOCK_MODE_R 22
+#define ICFG_SDIO0_CAP1__SPI_MODE_R 21
+#define ICFG_SDIO0_CAP1__CLK_MULT_R 13
+#define ICFG_SDIO0_CAP1__RETUNING_MODE_R 11
+#define ICFG_SDIO0_CAP1__TUNE_SDR50_R 10
+#define ICFG_SDIO0_CAP1__TIME_RETUNE_R 6
+#define ICFG_SDIO0_CAP1__DRIVER_D_R 5
+#define ICFG_SDIO0_CAP1__DRIVER_C_R 4
+#define ICFG_SDIO0_CAP1__DRIVER_A_R 3
+#define ICFG_SDIO0_CAP1__DDR50_R 2
+#define ICFG_SDIO0_CAP1__SDR104_R 1
+#define ICFG_SDIO0_CAP1__SDR50_R 0
+
+#define SDIO0_CTRL_REGS_BASE_ADDR (SDIO0_EMMCSDXC_SYSADDR)
+#define SDIO0_IDM_RESET_CTRL_ADDR (SDIO_IDM0_IDM_RESET_CONTROL)
+
+#define EMMC_CTRL_REGS_BASE_ADDR SDIO0_CTRL_REGS_BASE_ADDR
+#define EMMC_IDM_RESET_CTRL_ADDR SDIO0_IDM_RESET_CTRL_ADDR
+#define EMMC_IDM_IO_CTRL_DIRECT_ADDR SDIO_IDM0_IO_CONTROL_DIRECT
+
+extern struct emmc_global_buffer *emmc_global_buf_ptr;
+
+extern struct emmc_global_vars *emmc_global_vars_ptr;
+
+#define EMMC_CARD_DETECT_TIMEOUT_MS 1200
+#define EMMC_CMD_TIMEOUT_MS 200
+#define EMMC_BUSY_CMD_TIMEOUT_MS 200
+#define EMMC_CLOCK_SETTING_TIMEOUT_MS 100
+#define EMMC_WFE_RETRY 40000
+#define EMMC_WFE_RETRY_DELAY_US 10
+
+#ifdef EMMC_DEBUG
+#define EMMC_TRACE INFO
+#else
+#define EMMC_TRACE(...)
+#endif
+
+#endif /* EMMC_H */
diff --git a/include/drivers/brcm/emmc/emmc_api.h b/include/drivers/brcm/emmc/emmc_api.h
new file mode 100644
index 0000000000..c4c2a58035
--- /dev/null
+++ b/include/drivers/brcm/emmc/emmc_api.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2016 - 2020, Broadcom
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef EMMC_API_H
+#define EMMC_API_H
+
+#include "bcm_emmc.h"
+#include "emmc_pboot_hal_memory_drv.h"
+
+#ifdef INCLUDE_EMMC_DRIVER_ERASE_CODE
+/*
+ * The erasable unit of the eMMC is the Erase Group
+ * Erase group is measured in write blocks which
+ * are the basic writable units of the Device
+ * EMMC_ERASE_GROUP_SIZE is the number of writeable
+ * units (each unit is 512 bytes)
+ */
+
+/* Start address (sector) */
+#define EMMC_ERASE_START_BLOCK 0x0
+/* Number of blocks to be erased */
+#define EMMC_ERASE_BLOCK_COUNT 0x1
+
+#define EMMC_ERASE_USER_AREA 0
+#define EMMC_ERASE_BOOT_PARTITION1 1
+#define EMMC_ERASE_BOOT_PARTITION2 2
+
+/* eMMC partition to be erased */
+#define EMMC_ERASE_PARTITION EMMC_ERASE_USER_AREA
+#endif
+
+uint32_t bcm_emmc_init(bool card_rdy_only);
+void emmc_deinit(void);
+
+#ifdef INCLUDE_EMMC_DRIVER_ERASE_CODE
+int emmc_erase(uintptr_t mem_addr, size_t num_of_blocks, uint32_t partition);
+#endif
+
+uint32_t emmc_partition_select(uint32_t partition);
+uint32_t emmc_read(uintptr_t mem_addr, uintptr_t storage_addr,
+ size_t storage_size, size_t bytes_to_read);
+uint32_t emmc_write(uintptr_t mem_addr, uintptr_t data_addr,
+ size_t bytes_to_write);
+#endif /* EMMC_API_H */
diff --git a/include/drivers/brcm/emmc/emmc_brcm_rdb_sd4_top.h b/include/drivers/brcm/emmc/emmc_brcm_rdb_sd4_top.h
new file mode 100644
index 0000000000..96c333da4d
--- /dev/null
+++ b/include/drivers/brcm/emmc/emmc_brcm_rdb_sd4_top.h
@@ -0,0 +1,1116 @@
+/*
+ * Copyright (c) 2016 - 2020, Broadcom
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef BRCM_RDB_SD4_EMMC_TOP_H
+#define BRCM_RDB_SD4_EMMC_TOP_H
+
+#define SD4_EMMC_TOP_SYSADDR_OFFSET 0x00000000
+#define SD4_EMMC_TOP_SYSADDR_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_SYSADDR_TYPE uint32_t
+#define SD4_EMMC_TOP_SYSADDR_RESERVED_MASK 0x00000000
+#define SD4_EMMC_TOP_SYSADDR_SYSADDR_SHIFT 0
+#define SD4_EMMC_TOP_SYSADDR_SYSADDR_MASK 0xFFFFFFFF
+
+#define SD4_EMMC_TOP_BLOCK_OFFSET 0x00000004
+#define SD4_EMMC_TOP_BLOCK_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_BLOCK_TYPE uint32_t
+#define SD4_EMMC_TOP_BLOCK_RESERVED_MASK 0x00008000
+#define SD4_EMMC_TOP_BLOCK_BCNT_SHIFT 16
+#define SD4_EMMC_TOP_BLOCK_BCNT_MASK 0xFFFF0000
+#define SD4_EMMC_TOP_BLOCK_HSBS_SHIFT 12
+#define SD4_EMMC_TOP_BLOCK_HSBS_MASK 0x00007000
+#define SD4_EMMC_TOP_BLOCK_TBS_SHIFT 0
+#define SD4_EMMC_TOP_BLOCK_TBS_MASK 0x00000FFF
+
+#define SD4_EMMC_TOP_ARG_OFFSET 0x00000008
+#define SD4_EMMC_TOP_ARG_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_ARG_TYPE uint32_t
+#define SD4_EMMC_TOP_ARG_RESERVED_MASK 0x00000000
+#define SD4_EMMC_TOP_ARG_ARG_SHIFT 0
+#define SD4_EMMC_TOP_ARG_ARG_MASK 0xFFFFFFFF
+
+#define SD4_EMMC_TOP_CMD_OFFSET 0x0000000C
+#define SD4_EMMC_TOP_CMD_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_CMD_TYPE uint32_t
+#define SD4_EMMC_TOP_CMD_RESERVED_MASK 0xC004FFC0
+#define SD4_EMMC_TOP_CMD_CIDX_SHIFT 24
+#define SD4_EMMC_TOP_CMD_CIDX_MASK 0x3F000000
+#define SD4_EMMC_TOP_CMD_CTYP_SHIFT 22
+#define SD4_EMMC_TOP_CMD_CTYP_MASK 0x00C00000
+#define SD4_EMMC_TOP_CMD_DPS_SHIFT 21
+#define SD4_EMMC_TOP_CMD_DPS_MASK 0x00200000
+#define SD4_EMMC_TOP_CMD_CCHK_EN_SHIFT 20
+#define SD4_EMMC_TOP_CMD_CCHK_EN_MASK 0x00100000
+#define SD4_EMMC_TOP_CMD_CRC_EN_SHIFT 19
+#define SD4_EMMC_TOP_CMD_CRC_EN_MASK 0x00080000
+#define SD4_EMMC_TOP_CMD_RTSEL_SHIFT 16
+#define SD4_EMMC_TOP_CMD_RTSEL_MASK 0x00030000
+#define SD4_EMMC_TOP_CMD_MSBS_SHIFT 5
+#define SD4_EMMC_TOP_CMD_MSBS_MASK 0x00000020
+#define SD4_EMMC_TOP_CMD_DTDS_SHIFT 4
+#define SD4_EMMC_TOP_CMD_DTDS_MASK 0x00000010
+#define SD4_EMMC_TOP_CMD_ACMDEN_SHIFT 2
+#define SD4_EMMC_TOP_CMD_ACMDEN_MASK 0x0000000C
+#define SD4_EMMC_TOP_CMD_BCEN_SHIFT 1
+#define SD4_EMMC_TOP_CMD_BCEN_MASK 0x00000002
+#define SD4_EMMC_TOP_CMD_DMA_SHIFT 0
+#define SD4_EMMC_TOP_CMD_DMA_MASK 0x00000001
+
+#define SD4_EMMC_TOP_CMD_SD4_OFFSET 0x0000000C
+#define SD4_EMMC_TOP_CMD_SD4_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_CMD_SD4_TYPE uint32_t
+#define SD4_EMMC_TOP_CMD_SD4_RESERVED_MASK 0xC004FE00
+#define SD4_EMMC_TOP_CMD_SD4_CIDX_SHIFT 24
+#define SD4_EMMC_TOP_CMD_SD4_CIDX_MASK 0x3F000000
+#define SD4_EMMC_TOP_CMD_SD4_CTYP_SHIFT 22
+#define SD4_EMMC_TOP_CMD_SD4_CTYP_MASK 0x00C00000
+#define SD4_EMMC_TOP_CMD_SD4_DPS_SHIFT 21
+#define SD4_EMMC_TOP_CMD_SD4_DPS_MASK 0x00200000
+#define SD4_EMMC_TOP_CMD_SD4_CCHK_EN_SHIFT 20
+#define SD4_EMMC_TOP_CMD_SD4_CCHK_EN_MASK 0x00100000
+#define SD4_EMMC_TOP_CMD_SD4_CRC_EN_SHIFT 19
+#define SD4_EMMC_TOP_CMD_SD4_CRC_EN_MASK 0x00080000
+#define SD4_EMMC_TOP_CMD_SD4_RTSEL_SHIFT 16
+#define SD4_EMMC_TOP_CMD_SD4_RTSEL_MASK 0x00030000
+#define SD4_EMMC_TOP_CMD_SD4_RESPIRQDIS_SHIFT 8
+#define SD4_EMMC_TOP_CMD_SD4_RESPIRQDIS_MASK 0x00000100
+#define SD4_EMMC_TOP_CMD_SD4_RESPERRCHKEN_SHIFT 7
+#define SD4_EMMC_TOP_CMD_SD4_RESPERRCHKEN_MASK 0x00000080
+#define SD4_EMMC_TOP_CMD_SD4_RESPR1R5_SHIFT 6
+#define SD4_EMMC_TOP_CMD_SD4_RESPR1R5_MASK 0x00000040
+#define SD4_EMMC_TOP_CMD_SD4_MSBS_SHIFT 5
+#define SD4_EMMC_TOP_CMD_SD4_MSBS_MASK 0x00000020
+#define SD4_EMMC_TOP_CMD_SD4_DTDS_SHIFT 4
+#define SD4_EMMC_TOP_CMD_SD4_DTDS_MASK 0x00000010
+#define SD4_EMMC_TOP_CMD_SD4_ACMDEN_SHIFT 2
+#define SD4_EMMC_TOP_CMD_SD4_ACMDEN_MASK 0x0000000C
+#define SD4_EMMC_TOP_CMD_SD4_BCEN_SHIFT 1
+#define SD4_EMMC_TOP_CMD_SD4_BCEN_MASK 0x00000002
+#define SD4_EMMC_TOP_CMD_SD4_DMA_SHIFT 0
+#define SD4_EMMC_TOP_CMD_SD4_DMA_MASK 0x00000001
+
+#define SD4_EMMC_TOP_RESP0_OFFSET 0x00000010
+#define SD4_EMMC_TOP_RESP0_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_RESP0_TYPE uint32_t
+#define SD4_EMMC_TOP_RESP0_RESERVED_MASK 0x00000000
+#define SD4_EMMC_TOP_RESP0_RESP0_SHIFT 0
+#define SD4_EMMC_TOP_RESP0_RESP0_MASK 0xFFFFFFFF
+
+#define SD4_EMMC_TOP_RESP2_OFFSET 0x00000014
+#define SD4_EMMC_TOP_RESP2_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_RESP2_TYPE uint32_t
+#define SD4_EMMC_TOP_RESP2_RESERVED_MASK 0x00000000
+#define SD4_EMMC_TOP_RESP2_RESP2_SHIFT 0
+#define SD4_EMMC_TOP_RESP2_RESP2_MASK 0xFFFFFFFF
+
+#define SD4_EMMC_TOP_RESP4_OFFSET 0x00000018
+#define SD4_EMMC_TOP_RESP4_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_RESP4_TYPE uint32_t
+#define SD4_EMMC_TOP_RESP4_RESERVED_MASK 0x00000000
+#define SD4_EMMC_TOP_RESP4_RESP4_SHIFT 0
+#define SD4_EMMC_TOP_RESP4_RESP4_MASK 0xFFFFFFFF
+
+#define SD4_EMMC_TOP_RESP6_OFFSET 0x0000001C
+#define SD4_EMMC_TOP_RESP6_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_RESP6_TYPE uint32_t
+#define SD4_EMMC_TOP_RESP6_RESERVED_MASK 0x00000000
+#define SD4_EMMC_TOP_RESP6_RESP6_SHIFT 0
+#define SD4_EMMC_TOP_RESP6_RESP6_MASK 0xFFFFFFFF
+
+#define SD4_EMMC_TOP_BUFDAT_OFFSET 0x00000020
+#define SD4_EMMC_TOP_BUFDAT_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_BUFDAT_TYPE uint32_t
+#define SD4_EMMC_TOP_BUFDAT_RESERVED_MASK 0x00000000
+#define SD4_EMMC_TOP_BUFDAT_BUFDAT_SHIFT 0
+#define SD4_EMMC_TOP_BUFDAT_BUFDAT_MASK 0xFFFFFFFF
+
+#define SD4_EMMC_TOP_PSTATE_OFFSET 0x00000024
+#define SD4_EMMC_TOP_PSTATE_DEFAULT 0x1FFC0000
+#define SD4_EMMC_TOP_PSTATE_TYPE uint32_t
+#define SD4_EMMC_TOP_PSTATE_RESERVED_MASK 0xE000F0F0
+#define SD4_EMMC_TOP_PSTATE_DLS7_4_SHIFT 25
+#define SD4_EMMC_TOP_PSTATE_DLS7_4_MASK 0x1E000000
+#define SD4_EMMC_TOP_PSTATE_CLSL_SHIFT 24
+#define SD4_EMMC_TOP_PSTATE_CLSL_MASK 0x01000000
+#define SD4_EMMC_TOP_PSTATE_DLS3_0_SHIFT 20
+#define SD4_EMMC_TOP_PSTATE_DLS3_0_MASK 0x00F00000
+#define SD4_EMMC_TOP_PSTATE_WPSL_SHIFT 19
+#define SD4_EMMC_TOP_PSTATE_WPSL_MASK 0x00080000
+#define SD4_EMMC_TOP_PSTATE_CDPL_SHIFT 18
+#define SD4_EMMC_TOP_PSTATE_CDPL_MASK 0x00040000
+#define SD4_EMMC_TOP_PSTATE_CSS_SHIFT 17
+#define SD4_EMMC_TOP_PSTATE_CSS_MASK 0x00020000
+#define SD4_EMMC_TOP_PSTATE_CINS_SHIFT 16
+#define SD4_EMMC_TOP_PSTATE_CINS_MASK 0x00010000
+#define SD4_EMMC_TOP_PSTATE_BREN_SHIFT 11
+#define SD4_EMMC_TOP_PSTATE_BREN_MASK 0x00000800
+#define SD4_EMMC_TOP_PSTATE_BWEN_SHIFT 10
+#define SD4_EMMC_TOP_PSTATE_BWEN_MASK 0x00000400
+#define SD4_EMMC_TOP_PSTATE_RXACT_SHIFT 9
+#define SD4_EMMC_TOP_PSTATE_RXACT_MASK 0x00000200
+#define SD4_EMMC_TOP_PSTATE_WXACT_SHIFT 8
+#define SD4_EMMC_TOP_PSTATE_WXACT_MASK 0x00000100
+#define SD4_EMMC_TOP_PSTATE_RETUNE_REQ_SHIFT 3
+#define SD4_EMMC_TOP_PSTATE_RETUNE_REQ_MASK 0x00000008
+#define SD4_EMMC_TOP_PSTATE_DATACT_SHIFT 2
+#define SD4_EMMC_TOP_PSTATE_DATACT_MASK 0x00000004
+#define SD4_EMMC_TOP_PSTATE_DATINH_SHIFT 1
+#define SD4_EMMC_TOP_PSTATE_DATINH_MASK 0x00000002
+#define SD4_EMMC_TOP_PSTATE_CMDINH_SHIFT 0
+#define SD4_EMMC_TOP_PSTATE_CMDINH_MASK 0x00000001
+
+#define SD4_EMMC_TOP_PSTATE_SD4_OFFSET 0x00000024
+#define SD4_EMMC_TOP_PSTATE_SD4_DEFAULT 0x01FC00F0
+#define SD4_EMMC_TOP_PSTATE_SD4_TYPE uint32_t
+#define SD4_EMMC_TOP_PSTATE_SD4_RESERVED_MASK 0x1E00F000
+#define SD4_EMMC_TOP_PSTATE_SD4_STBLDET_SHIFT 31
+#define SD4_EMMC_TOP_PSTATE_SD4_STBLDET_MASK 0x80000000
+#define SD4_EMMC_TOP_PSTATE_SD4_LANESYNC_SHIFT 30
+#define SD4_EMMC_TOP_PSTATE_SD4_LANESYNC_MASK 0x40000000
+#define SD4_EMMC_TOP_PSTATE_SD4_INDORMNTSTATE_SHIFT 29
+#define SD4_EMMC_TOP_PSTATE_SD4_INDORMNTSTATE_MASK 0x20000000
+#define SD4_EMMC_TOP_PSTATE_SD4_CLSL_SHIFT 24
+#define SD4_EMMC_TOP_PSTATE_SD4_CLSL_MASK 0x01000000
+#define SD4_EMMC_TOP_PSTATE_SD4_DLS3_0_SHIFT 20
+#define SD4_EMMC_TOP_PSTATE_SD4_DLS3_0_MASK 0x00F00000
+#define SD4_EMMC_TOP_PSTATE_SD4_WPSL_SHIFT 19
+#define SD4_EMMC_TOP_PSTATE_SD4_WPSL_MASK 0x00080000
+#define SD4_EMMC_TOP_PSTATE_SD4_CDPL_SHIFT 18
+#define SD4_EMMC_TOP_PSTATE_SD4_CDPL_MASK 0x00040000
+#define SD4_EMMC_TOP_PSTATE_SD4_CSS_SHIFT 17
+#define SD4_EMMC_TOP_PSTATE_SD4_CSS_MASK 0x00020000
+#define SD4_EMMC_TOP_PSTATE_SD4_CINS_SHIFT 16
+#define SD4_EMMC_TOP_PSTATE_SD4_CINS_MASK 0x00010000
+#define SD4_EMMC_TOP_PSTATE_SD4_BREN_SHIFT 11
+#define SD4_EMMC_TOP_PSTATE_SD4_BREN_MASK 0x00000800
+#define SD4_EMMC_TOP_PSTATE_SD4_BWEN_SHIFT 10
+#define SD4_EMMC_TOP_PSTATE_SD4_BWEN_MASK 0x00000400
+#define SD4_EMMC_TOP_PSTATE_SD4_RXACT_SHIFT 9
+#define SD4_EMMC_TOP_PSTATE_SD4_RXACT_MASK 0x00000200
+#define SD4_EMMC_TOP_PSTATE_SD4_WXACT_SHIFT 8
+#define SD4_EMMC_TOP_PSTATE_SD4_WXACT_MASK 0x00000100
+#define SD4_EMMC_TOP_PSTATE_SD4_DLS7_4_SHIFT 4
+#define SD4_EMMC_TOP_PSTATE_SD4_DLS7_4_MASK 0x000000F0
+#define SD4_EMMC_TOP_PSTATE_SD4_RETUNE_REQ_SHIFT 3
+#define SD4_EMMC_TOP_PSTATE_SD4_RETUNE_REQ_MASK 0x00000008
+#define SD4_EMMC_TOP_PSTATE_SD4_DATACT_SHIFT 2
+#define SD4_EMMC_TOP_PSTATE_SD4_DATACT_MASK 0x00000004
+#define SD4_EMMC_TOP_PSTATE_SD4_DATINH_SHIFT 1
+#define SD4_EMMC_TOP_PSTATE_SD4_DATINH_MASK 0x00000002
+#define SD4_EMMC_TOP_PSTATE_SD4_CMDINH_SHIFT 0
+#define SD4_EMMC_TOP_PSTATE_SD4_CMDINH_MASK 0x00000001
+
+#define SD4_EMMC_TOP_CTRL_OFFSET 0x00000028
+#define SD4_EMMC_TOP_CTRL_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_CTRL_TYPE uint32_t
+#define SD4_EMMC_TOP_CTRL_RESERVED_MASK 0xF800E000
+#define SD4_EMMC_TOP_CTRL_WAKENRMV_SHIFT 26
+#define SD4_EMMC_TOP_CTRL_WAKENRMV_MASK 0x04000000
+#define SD4_EMMC_TOP_CTRL_WAKENINS_SHIFT 25
+#define SD4_EMMC_TOP_CTRL_WAKENINS_MASK 0x02000000
+#define SD4_EMMC_TOP_CTRL_WAKENIRQ_SHIFT 24
+#define SD4_EMMC_TOP_CTRL_WAKENIRQ_MASK 0x01000000
+#define SD4_EMMC_TOP_CTRL_BOOTACK_SHIFT 23
+#define SD4_EMMC_TOP_CTRL_BOOTACK_MASK 0x00800000
+#define SD4_EMMC_TOP_CTRL_ATLBOOTEN_SHIFT 22
+#define SD4_EMMC_TOP_CTRL_ATLBOOTEN_MASK 0x00400000
+#define SD4_EMMC_TOP_CTRL_BOOTEN_SHIFT 21
+#define SD4_EMMC_TOP_CTRL_BOOTEN_MASK 0x00200000
+#define SD4_EMMC_TOP_CTRL_SPIMODE_SHIFT 20
+#define SD4_EMMC_TOP_CTRL_SPIMODE_MASK 0x00100000
+#define SD4_EMMC_TOP_CTRL_BLKIRQ_SHIFT 19
+#define SD4_EMMC_TOP_CTRL_BLKIRQ_MASK 0x00080000
+#define SD4_EMMC_TOP_CTRL_RDWTCRTL_SHIFT 18
+#define SD4_EMMC_TOP_CTRL_RDWTCRTL_MASK 0x00040000
+#define SD4_EMMC_TOP_CTRL_CONTREQ_SHIFT 17
+#define SD4_EMMC_TOP_CTRL_CONTREQ_MASK 0x00020000
+#define SD4_EMMC_TOP_CTRL_BLKSTPREQ_SHIFT 16
+#define SD4_EMMC_TOP_CTRL_BLKSTPREQ_MASK 0x00010000
+#define SD4_EMMC_TOP_CTRL_HRESET_SHIFT 12
+#define SD4_EMMC_TOP_CTRL_HRESET_MASK 0x00001000
+#define SD4_EMMC_TOP_CTRL_SDVSELVDD1_SHIFT 9
+#define SD4_EMMC_TOP_CTRL_SDVSELVDD1_MASK 0x00000E00
+#define SD4_EMMC_TOP_CTRL_SDPWR_SHIFT 8
+#define SD4_EMMC_TOP_CTRL_SDPWR_MASK 0x00000100
+#define SD4_EMMC_TOP_CTRL_CDSD_SHIFT 7
+#define SD4_EMMC_TOP_CTRL_CDSD_MASK 0x00000080
+#define SD4_EMMC_TOP_CTRL_CDTL_SHIFT 6
+#define SD4_EMMC_TOP_CTRL_CDTL_MASK 0x00000040
+#define SD4_EMMC_TOP_CTRL_SDB_SHIFT 5
+#define SD4_EMMC_TOP_CTRL_SDB_MASK 0x00000020
+#define SD4_EMMC_TOP_CTRL_DMASEL_SHIFT 3
+#define SD4_EMMC_TOP_CTRL_DMASEL_MASK 0x00000018
+#define SD4_EMMC_TOP_CTRL_HSEN_SHIFT 2
+#define SD4_EMMC_TOP_CTRL_HSEN_MASK 0x00000004
+#define SD4_EMMC_TOP_CTRL_DXTW_SHIFT 1
+#define SD4_EMMC_TOP_CTRL_DXTW_MASK 0x00000002
+#define SD4_EMMC_TOP_CTRL_LEDCTL_SHIFT 0
+#define SD4_EMMC_TOP_CTRL_LEDCTL_MASK 0x00000001
+
+#define SD4_EMMC_TOP_CTRL_SD4_OFFSET 0x00000028
+#define SD4_EMMC_TOP_CTRL_SD4_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_CTRL_SD4_TYPE uint32_t
+#define SD4_EMMC_TOP_CTRL_SD4_RESERVED_MASK 0xF8F00000
+#define SD4_EMMC_TOP_CTRL_SD4_WAKENRMV_SHIFT 26
+#define SD4_EMMC_TOP_CTRL_SD4_WAKENRMV_MASK 0x04000000
+#define SD4_EMMC_TOP_CTRL_SD4_WAKENINS_SHIFT 25
+#define SD4_EMMC_TOP_CTRL_SD4_WAKENINS_MASK 0x02000000
+#define SD4_EMMC_TOP_CTRL_SD4_WAKENIRQ_SHIFT 24
+#define SD4_EMMC_TOP_CTRL_SD4_WAKENIRQ_MASK 0x01000000
+#define SD4_EMMC_TOP_CTRL_SD4_BLKIRQ_SHIFT 19
+#define SD4_EMMC_TOP_CTRL_SD4_BLKIRQ_MASK 0x00080000
+#define SD4_EMMC_TOP_CTRL_SD4_RDWTCRTL_SHIFT 18
+#define SD4_EMMC_TOP_CTRL_SD4_RDWTCRTL_MASK 0x00040000
+#define SD4_EMMC_TOP_CTRL_SD4_CONTREQ_SHIFT 17
+#define SD4_EMMC_TOP_CTRL_SD4_CONTREQ_MASK 0x00020000
+#define SD4_EMMC_TOP_CTRL_SD4_BLKSTPREQ_SHIFT 16
+#define SD4_EMMC_TOP_CTRL_SD4_BLKSTPREQ_MASK 0x00010000
+#define SD4_EMMC_TOP_CTRL_SD4_SDVSELVDD2_SHIFT 13
+#define SD4_EMMC_TOP_CTRL_SD4_SDVSELVDD2_MASK 0x0000E000
+#define SD4_EMMC_TOP_CTRL_SD4_SDPWRVDD2_SHIFT 12
+#define SD4_EMMC_TOP_CTRL_SD4_SDPWRVDD2_MASK 0x00001000
+#define SD4_EMMC_TOP_CTRL_SD4_SDVSELVDD1_SHIFT 9
+#define SD4_EMMC_TOP_CTRL_SD4_SDVSELVDD1_MASK 0x00000E00
+#define SD4_EMMC_TOP_CTRL_SD4_SDPWR_SHIFT 8
+#define SD4_EMMC_TOP_CTRL_SD4_SDPWR_MASK 0x00000100
+#define SD4_EMMC_TOP_CTRL_SD4_CDSD_SHIFT 7
+#define SD4_EMMC_TOP_CTRL_SD4_CDSD_MASK 0x00000080
+#define SD4_EMMC_TOP_CTRL_SD4_CDTL_SHIFT 6
+#define SD4_EMMC_TOP_CTRL_SD4_CDTL_MASK 0x00000040
+#define SD4_EMMC_TOP_CTRL_SD4_SDB_SHIFT 5
+#define SD4_EMMC_TOP_CTRL_SD4_SDB_MASK 0x00000020
+#define SD4_EMMC_TOP_CTRL_SD4_DMASEL_SHIFT 3
+#define SD4_EMMC_TOP_CTRL_SD4_DMASEL_MASK 0x00000018
+#define SD4_EMMC_TOP_CTRL_SD4_HSEN_SHIFT 2
+#define SD4_EMMC_TOP_CTRL_SD4_HSEN_MASK 0x00000004
+#define SD4_EMMC_TOP_CTRL_SD4_DXTW_SHIFT 1
+#define SD4_EMMC_TOP_CTRL_SD4_DXTW_MASK 0x00000002
+#define SD4_EMMC_TOP_CTRL_SD4_LEDCTL_SHIFT 0
+#define SD4_EMMC_TOP_CTRL_SD4_LEDCTL_MASK 0x00000001
+
+#define SD4_EMMC_TOP_CTRL1_OFFSET 0x0000002C
+#define SD4_EMMC_TOP_CTRL1_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_CTRL1_TYPE uint32_t
+#define SD4_EMMC_TOP_CTRL1_RESERVED_MASK 0xF8F00018
+#define SD4_EMMC_TOP_CTRL1_DATRST_SHIFT 26
+#define SD4_EMMC_TOP_CTRL1_DATRST_MASK 0x04000000
+#define SD4_EMMC_TOP_CTRL1_CMDRST_SHIFT 25
+#define SD4_EMMC_TOP_CTRL1_CMDRST_MASK 0x02000000
+#define SD4_EMMC_TOP_CTRL1_RST_SHIFT 24
+#define SD4_EMMC_TOP_CTRL1_RST_MASK 0x01000000
+#define SD4_EMMC_TOP_CTRL1_DTCNT_SHIFT 16
+#define SD4_EMMC_TOP_CTRL1_DTCNT_MASK 0x000F0000
+#define SD4_EMMC_TOP_CTRL1_SDCLKSEL_SHIFT 8
+#define SD4_EMMC_TOP_CTRL1_SDCLKSEL_MASK 0x0000FF00
+#define SD4_EMMC_TOP_CTRL1_SDCLKSEL_UP_SHIFT 6
+#define SD4_EMMC_TOP_CTRL1_SDCLKSEL_UP_MASK 0x000000C0
+#define SD4_EMMC_TOP_CTRL1_CLKGENSEL_SHIFT 5
+#define SD4_EMMC_TOP_CTRL1_CLKGENSEL_MASK 0x00000020
+#define SD4_EMMC_TOP_CTRL1_SDCLKEN_SHIFT 2
+#define SD4_EMMC_TOP_CTRL1_SDCLKEN_MASK 0x00000004
+#define SD4_EMMC_TOP_CTRL1_ICLKSTB_SHIFT 1
+#define SD4_EMMC_TOP_CTRL1_ICLKSTB_MASK 0x00000002
+#define SD4_EMMC_TOP_CTRL1_ICLKEN_SHIFT 0
+#define SD4_EMMC_TOP_CTRL1_ICLKEN_MASK 0x00000001
+
+#define SD4_EMMC_TOP_INTR_OFFSET 0x00000030
+#define SD4_EMMC_TOP_INTR_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_INTR_TYPE uint32_t
+#define SD4_EMMC_TOP_INTR_RESERVED_MASK 0xEC000000
+#define SD4_EMMC_TOP_INTR_TRESPERR_SHIFT 28
+#define SD4_EMMC_TOP_INTR_TRESPERR_MASK 0x10000000
+#define SD4_EMMC_TOP_INTR_ADMAERR_SHIFT 25
+#define SD4_EMMC_TOP_INTR_ADMAERR_MASK 0x02000000
+#define SD4_EMMC_TOP_INTR_CMDERROR_SHIFT 24
+#define SD4_EMMC_TOP_INTR_CMDERROR_MASK 0x01000000
+#define SD4_EMMC_TOP_INTR_IERR_SHIFT 23
+#define SD4_EMMC_TOP_INTR_IERR_MASK 0x00800000
+#define SD4_EMMC_TOP_INTR_DEBERR_SHIFT 22
+#define SD4_EMMC_TOP_INTR_DEBERR_MASK 0x00400000
+#define SD4_EMMC_TOP_INTR_DCRCERR_SHIFT 21
+#define SD4_EMMC_TOP_INTR_DCRCERR_MASK 0x00200000
+#define SD4_EMMC_TOP_INTR_DTOERR_SHIFT 20
+#define SD4_EMMC_TOP_INTR_DTOERR_MASK 0x00100000
+#define SD4_EMMC_TOP_INTR_CMDIDXERR_SHIFT 19
+#define SD4_EMMC_TOP_INTR_CMDIDXERR_MASK 0x00080000
+#define SD4_EMMC_TOP_INTR_CEBERR_SHIFT 18
+#define SD4_EMMC_TOP_INTR_CEBERR_MASK 0x00040000
+#define SD4_EMMC_TOP_INTR_CCRCERR_SHIFT 17
+#define SD4_EMMC_TOP_INTR_CCRCERR_MASK 0x00020000
+#define SD4_EMMC_TOP_INTR_CTOERR_SHIFT 16
+#define SD4_EMMC_TOP_INTR_CTOERR_MASK 0x00010000
+#define SD4_EMMC_TOP_INTR_ERRIRQ_SHIFT 15
+#define SD4_EMMC_TOP_INTR_ERRIRQ_MASK 0x00008000
+#define SD4_EMMC_TOP_INTR_BTIRQ_SHIFT 14
+#define SD4_EMMC_TOP_INTR_BTIRQ_MASK 0x00004000
+#define SD4_EMMC_TOP_INTR_BTACKRX_SHIFT 13
+#define SD4_EMMC_TOP_INTR_BTACKRX_MASK 0x00002000
+#define SD4_EMMC_TOP_INTR_RETUNE_EVENT_SHIFT 12
+#define SD4_EMMC_TOP_INTR_RETUNE_EVENT_MASK 0x00001000
+#define SD4_EMMC_TOP_INTR_INT_C_SHIFT 11
+#define SD4_EMMC_TOP_INTR_INT_C_MASK 0x00000800
+#define SD4_EMMC_TOP_INTR_INT_B_SHIFT 10
+#define SD4_EMMC_TOP_INTR_INT_B_MASK 0x00000400
+#define SD4_EMMC_TOP_INTR_INT_A_SHIFT 9
+#define SD4_EMMC_TOP_INTR_INT_A_MASK 0x00000200
+#define SD4_EMMC_TOP_INTR_CRDIRQ_SHIFT 8
+#define SD4_EMMC_TOP_INTR_CRDIRQ_MASK 0x00000100
+#define SD4_EMMC_TOP_INTR_CRDRMV_SHIFT 7
+#define SD4_EMMC_TOP_INTR_CRDRMV_MASK 0x00000080
+#define SD4_EMMC_TOP_INTR_CRDINS_SHIFT 6
+#define SD4_EMMC_TOP_INTR_CRDINS_MASK 0x00000040
+#define SD4_EMMC_TOP_INTR_BRRDY_SHIFT 5
+#define SD4_EMMC_TOP_INTR_BRRDY_MASK 0x00000020
+#define SD4_EMMC_TOP_INTR_BWRDY_SHIFT 4
+#define SD4_EMMC_TOP_INTR_BWRDY_MASK 0x00000010
+#define SD4_EMMC_TOP_INTR_DMAIRQ_SHIFT 3
+#define SD4_EMMC_TOP_INTR_DMAIRQ_MASK 0x00000008
+#define SD4_EMMC_TOP_INTR_BLKENT_SHIFT 2
+#define SD4_EMMC_TOP_INTR_BLKENT_MASK 0x00000004
+#define SD4_EMMC_TOP_INTR_TXDONE_SHIFT 1
+#define SD4_EMMC_TOP_INTR_TXDONE_MASK 0x00000002
+#define SD4_EMMC_TOP_INTR_CMDDONE_SHIFT 0
+#define SD4_EMMC_TOP_INTR_CMDDONE_MASK 0x00000001
+
+#define SD4_EMMC_TOP_INTR_SD4_OFFSET 0x00000030
+#define SD4_EMMC_TOP_INTR_SD4_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_INTR_SD4_TYPE uint32_t
+#define SD4_EMMC_TOP_INTR_SD4_RESERVED_MASK 0xF0006000
+#define SD4_EMMC_TOP_INTR_SD4_TRESPERR_SHIFT 27
+#define SD4_EMMC_TOP_INTR_SD4_TRESPERR_MASK 0x08000000
+#define SD4_EMMC_TOP_INTR_SD4_TUNEERR_SHIFT 26
+#define SD4_EMMC_TOP_INTR_SD4_TUNEERR_MASK 0x04000000
+#define SD4_EMMC_TOP_INTR_SD4_ADMAERR_SHIFT 25
+#define SD4_EMMC_TOP_INTR_SD4_ADMAERR_MASK 0x02000000
+#define SD4_EMMC_TOP_INTR_SD4_CMDERROR_SHIFT 24
+#define SD4_EMMC_TOP_INTR_SD4_CMDERROR_MASK 0x01000000
+#define SD4_EMMC_TOP_INTR_SD4_IERR_SHIFT 23
+#define SD4_EMMC_TOP_INTR_SD4_IERR_MASK 0x00800000
+#define SD4_EMMC_TOP_INTR_SD4_DEBERR_SHIFT 22
+#define SD4_EMMC_TOP_INTR_SD4_DEBERR_MASK 0x00400000
+#define SD4_EMMC_TOP_INTR_SD4_DCRCERR_SHIFT 21
+#define SD4_EMMC_TOP_INTR_SD4_DCRCERR_MASK 0x00200000
+#define SD4_EMMC_TOP_INTR_SD4_DTOERR_SHIFT 20
+#define SD4_EMMC_TOP_INTR_SD4_DTOERR_MASK 0x00100000
+#define SD4_EMMC_TOP_INTR_SD4_CMDIDXERR_SHIFT 19
+#define SD4_EMMC_TOP_INTR_SD4_CMDIDXERR_MASK 0x00080000
+#define SD4_EMMC_TOP_INTR_SD4_CEBERR_SHIFT 18
+#define SD4_EMMC_TOP_INTR_SD4_CEBERR_MASK 0x00040000
+#define SD4_EMMC_TOP_INTR_SD4_CCRCERR_SHIFT 17
+#define SD4_EMMC_TOP_INTR_SD4_CCRCERR_MASK 0x00020000
+#define SD4_EMMC_TOP_INTR_SD4_CTOERR_SHIFT 16
+#define SD4_EMMC_TOP_INTR_SD4_CTOERR_MASK 0x00010000
+#define SD4_EMMC_TOP_INTR_SD4_ERRIRQ_SHIFT 15
+#define SD4_EMMC_TOP_INTR_SD4_ERRIRQ_MASK 0x00008000
+#define SD4_EMMC_TOP_INTR_SD4_RETUNE_EVENT_SHIFT 12
+#define SD4_EMMC_TOP_INTR_SD4_RETUNE_EVENT_MASK 0x00001000
+#define SD4_EMMC_TOP_INTR_SD4_INT_C_SHIFT 11
+#define SD4_EMMC_TOP_INTR_SD4_INT_C_MASK 0x00000800
+#define SD4_EMMC_TOP_INTR_SD4_INT_B_SHIFT 10
+#define SD4_EMMC_TOP_INTR_SD4_INT_B_MASK 0x00000400
+#define SD4_EMMC_TOP_INTR_SD4_INT_A_SHIFT 9
+#define SD4_EMMC_TOP_INTR_SD4_INT_A_MASK 0x00000200
+#define SD4_EMMC_TOP_INTR_SD4_CRDIRQ_SHIFT 8
+#define SD4_EMMC_TOP_INTR_SD4_CRDIRQ_MASK 0x00000100
+#define SD4_EMMC_TOP_INTR_SD4_CRDRMV_SHIFT 7
+#define SD4_EMMC_TOP_INTR_SD4_CRDRMV_MASK 0x00000080
+#define SD4_EMMC_TOP_INTR_SD4_CRDINS_SHIFT 6
+#define SD4_EMMC_TOP_INTR_SD4_CRDINS_MASK 0x00000040
+#define SD4_EMMC_TOP_INTR_SD4_BRRDY_SHIFT 5
+#define SD4_EMMC_TOP_INTR_SD4_BRRDY_MASK 0x00000020
+#define SD4_EMMC_TOP_INTR_SD4_BWRDY_SHIFT 4
+#define SD4_EMMC_TOP_INTR_SD4_BWRDY_MASK 0x00000010
+#define SD4_EMMC_TOP_INTR_SD4_DMAIRQ_SHIFT 3
+#define SD4_EMMC_TOP_INTR_SD4_DMAIRQ_MASK 0x00000008
+#define SD4_EMMC_TOP_INTR_SD4_BLKENT_SHIFT 2
+#define SD4_EMMC_TOP_INTR_SD4_BLKENT_MASK 0x00000004
+#define SD4_EMMC_TOP_INTR_SD4_TXDONE_SHIFT 1
+#define SD4_EMMC_TOP_INTR_SD4_TXDONE_MASK 0x00000002
+#define SD4_EMMC_TOP_INTR_SD4_CMDDONE_SHIFT 0
+#define SD4_EMMC_TOP_INTR_SD4_CMDDONE_MASK 0x00000001
+
+#define SD4_EMMC_TOP_INTREN1_OFFSET 0x00000034
+#define SD4_EMMC_TOP_INTREN1_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_INTREN1_TYPE uint32_t
+#define SD4_EMMC_TOP_INTREN1_RESERVED_MASK 0xEC000000
+#define SD4_EMMC_TOP_INTREN1_TRESPERREN_SHIFT 28
+#define SD4_EMMC_TOP_INTREN1_TRESPERREN_MASK 0x10000000
+#define SD4_EMMC_TOP_INTREN1_ADMAEREN_SHIFT 25
+#define SD4_EMMC_TOP_INTREN1_ADMAEREN_MASK 0x02000000
+#define SD4_EMMC_TOP_INTREN1_CMDERREN_SHIFT 24
+#define SD4_EMMC_TOP_INTREN1_CMDERREN_MASK 0x01000000
+#define SD4_EMMC_TOP_INTREN1_ILIMERREN_SHIFT 23
+#define SD4_EMMC_TOP_INTREN1_ILIMERREN_MASK 0x00800000
+#define SD4_EMMC_TOP_INTREN1_DEBERREN_SHIFT 22
+#define SD4_EMMC_TOP_INTREN1_DEBERREN_MASK 0x00400000
+#define SD4_EMMC_TOP_INTREN1_DCRCERREN_SHIFT 21
+#define SD4_EMMC_TOP_INTREN1_DCRCERREN_MASK 0x00200000
+#define SD4_EMMC_TOP_INTREN1_DTOERREN_SHIFT 20
+#define SD4_EMMC_TOP_INTREN1_DTOERREN_MASK 0x00100000
+#define SD4_EMMC_TOP_INTREN1_CIDXERREN_SHIFT 19
+#define SD4_EMMC_TOP_INTREN1_CIDXERREN_MASK 0x00080000
+#define SD4_EMMC_TOP_INTREN1_CEBERREN_SHIFT 18
+#define SD4_EMMC_TOP_INTREN1_CEBERREN_MASK 0x00040000
+#define SD4_EMMC_TOP_INTREN1_CMDCRCEN_SHIFT 17
+#define SD4_EMMC_TOP_INTREN1_CMDCRCEN_MASK 0x00020000
+#define SD4_EMMC_TOP_INTREN1_CMDTOEN_SHIFT 16
+#define SD4_EMMC_TOP_INTREN1_CMDTOEN_MASK 0x00010000
+#define SD4_EMMC_TOP_INTREN1_FIXZ_SHIFT 15
+#define SD4_EMMC_TOP_INTREN1_FIXZ_MASK 0x00008000
+#define SD4_EMMC_TOP_INTREN1_BTIRQEN_SHIFT 14
+#define SD4_EMMC_TOP_INTREN1_BTIRQEN_MASK 0x00004000
+#define SD4_EMMC_TOP_INTREN1_BTACKRXEN_SHIFT 13
+#define SD4_EMMC_TOP_INTREN1_BTACKRXEN_MASK 0x00002000
+#define SD4_EMMC_TOP_INTREN1_RETUNE_EVENTEN_SHIFT 12
+#define SD4_EMMC_TOP_INTREN1_RETUNE_EVENTEN_MASK 0x00001000
+#define SD4_EMMC_TOP_INTREN1_INT_C_EN_SHIFT 11
+#define SD4_EMMC_TOP_INTREN1_INT_C_EN_MASK 0x00000800
+#define SD4_EMMC_TOP_INTREN1_INT_B_EN_SHIFT 10
+#define SD4_EMMC_TOP_INTREN1_INT_B_EN_MASK 0x00000400
+#define SD4_EMMC_TOP_INTREN1_INT_A_EN_SHIFT 9
+#define SD4_EMMC_TOP_INTREN1_INT_A_EN_MASK 0x00000200
+#define SD4_EMMC_TOP_INTREN1_CIRQEN_SHIFT 8
+#define SD4_EMMC_TOP_INTREN1_CIRQEN_MASK 0x00000100
+#define SD4_EMMC_TOP_INTREN1_CRDRMVEN_SHIFT 7
+#define SD4_EMMC_TOP_INTREN1_CRDRMVEN_MASK 0x00000080
+#define SD4_EMMC_TOP_INTREN1_CRDINSEN_SHIFT 6
+#define SD4_EMMC_TOP_INTREN1_CRDINSEN_MASK 0x00000040
+#define SD4_EMMC_TOP_INTREN1_BUFRREN_SHIFT 5
+#define SD4_EMMC_TOP_INTREN1_BUFRREN_MASK 0x00000020
+#define SD4_EMMC_TOP_INTREN1_BUFWREN_SHIFT 4
+#define SD4_EMMC_TOP_INTREN1_BUFWREN_MASK 0x00000010
+#define SD4_EMMC_TOP_INTREN1_DMAIRQEN_SHIFT 3
+#define SD4_EMMC_TOP_INTREN1_DMAIRQEN_MASK 0x00000008
+#define SD4_EMMC_TOP_INTREN1_BLKEN_SHIFT 2
+#define SD4_EMMC_TOP_INTREN1_BLKEN_MASK 0x00000004
+#define SD4_EMMC_TOP_INTREN1_TXDONEEN_SHIFT 1
+#define SD4_EMMC_TOP_INTREN1_TXDONEEN_MASK 0x00000002
+#define SD4_EMMC_TOP_INTREN1_CMDDONEEN_SHIFT 0
+#define SD4_EMMC_TOP_INTREN1_CMDDONEEN_MASK 0x00000001
+
+#define SD4_EMMC_TOP_INTREN1_SD4_OFFSET 0x00000034
+#define SD4_EMMC_TOP_INTREN1_SD4_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_INTREN1_SD4_TYPE uint32_t
+#define SD4_EMMC_TOP_INTREN1_SD4_RESERVED_MASK 0x00006000
+#define SD4_EMMC_TOP_INTREN1_SD4_VNDRERREN_SHIFT 28
+#define SD4_EMMC_TOP_INTREN1_SD4_VNDRERREN_MASK 0xF0000000
+#define SD4_EMMC_TOP_INTREN1_SD4_TRESPERREN_SHIFT 27
+#define SD4_EMMC_TOP_INTREN1_SD4_TRESPERREN_MASK 0x08000000
+#define SD4_EMMC_TOP_INTREN1_SD4_TUNEERREN_SHIFT 26
+#define SD4_EMMC_TOP_INTREN1_SD4_TUNEERREN_MASK 0x04000000
+#define SD4_EMMC_TOP_INTREN1_SD4_ADMAEREN_SHIFT 25
+#define SD4_EMMC_TOP_INTREN1_SD4_ADMAEREN_MASK 0x02000000
+#define SD4_EMMC_TOP_INTREN1_SD4_CMDERREN_SHIFT 24
+#define SD4_EMMC_TOP_INTREN1_SD4_CMDERREN_MASK 0x01000000
+#define SD4_EMMC_TOP_INTREN1_SD4_ILIMERREN_SHIFT 23
+#define SD4_EMMC_TOP_INTREN1_SD4_ILIMERREN_MASK 0x00800000
+#define SD4_EMMC_TOP_INTREN1_SD4_DEBERREN_SHIFT 22
+#define SD4_EMMC_TOP_INTREN1_SD4_DEBERREN_MASK 0x00400000
+#define SD4_EMMC_TOP_INTREN1_SD4_DCRCERREN_SHIFT 21
+#define SD4_EMMC_TOP_INTREN1_SD4_DCRCERREN_MASK 0x00200000
+#define SD4_EMMC_TOP_INTREN1_SD4_DTOERREN_SHIFT 20
+#define SD4_EMMC_TOP_INTREN1_SD4_DTOERREN_MASK 0x00100000
+#define SD4_EMMC_TOP_INTREN1_SD4_CIDXERREN_SHIFT 19
+#define SD4_EMMC_TOP_INTREN1_SD4_CIDXERREN_MASK 0x00080000
+#define SD4_EMMC_TOP_INTREN1_SD4_CEBERREN_SHIFT 18
+#define SD4_EMMC_TOP_INTREN1_SD4_CEBERREN_MASK 0x00040000
+#define SD4_EMMC_TOP_INTREN1_SD4_CMDCRCEN_SHIFT 17
+#define SD4_EMMC_TOP_INTREN1_SD4_CMDCRCEN_MASK 0x00020000
+#define SD4_EMMC_TOP_INTREN1_SD4_CMDTOEN_SHIFT 16
+#define SD4_EMMC_TOP_INTREN1_SD4_CMDTOEN_MASK 0x00010000
+#define SD4_EMMC_TOP_INTREN1_SD4_FIXZ_SHIFT 15
+#define SD4_EMMC_TOP_INTREN1_SD4_FIXZ_MASK 0x00008000
+#define SD4_EMMC_TOP_INTREN1_SD4_RETUNE_EVENTEN_SHIFT 12
+#define SD4_EMMC_TOP_INTREN1_SD4_RETUNE_EVENTEN_MASK 0x00001000
+#define SD4_EMMC_TOP_INTREN1_SD4_INT_C_EN_SHIFT 11
+#define SD4_EMMC_TOP_INTREN1_SD4_INT_C_EN_MASK 0x00000800
+#define SD4_EMMC_TOP_INTREN1_SD4_INT_B_EN_SHIFT 10
+#define SD4_EMMC_TOP_INTREN1_SD4_INT_B_EN_MASK 0x00000400
+#define SD4_EMMC_TOP_INTREN1_SD4_INT_A_EN_SHIFT 9
+#define SD4_EMMC_TOP_INTREN1_SD4_INT_A_EN_MASK 0x00000200
+#define SD4_EMMC_TOP_INTREN1_SD4_CIRQEN_SHIFT 8
+#define SD4_EMMC_TOP_INTREN1_SD4_CIRQEN_MASK 0x00000100
+#define SD4_EMMC_TOP_INTREN1_SD4_CRDRMVEN_SHIFT 7
+#define SD4_EMMC_TOP_INTREN1_SD4_CRDRMVEN_MASK 0x00000080
+#define SD4_EMMC_TOP_INTREN1_SD4_CRDINSEN_SHIFT 6
+#define SD4_EMMC_TOP_INTREN1_SD4_CRDINSEN_MASK 0x00000040
+#define SD4_EMMC_TOP_INTREN1_SD4_BUFRREN_SHIFT 5
+#define SD4_EMMC_TOP_INTREN1_SD4_BUFRREN_MASK 0x00000020
+#define SD4_EMMC_TOP_INTREN1_SD4_BUFWREN_SHIFT 4
+#define SD4_EMMC_TOP_INTREN1_SD4_BUFWREN_MASK 0x00000010
+#define SD4_EMMC_TOP_INTREN1_SD4_DMAIRQEN_SHIFT 3
+#define SD4_EMMC_TOP_INTREN1_SD4_DMAIRQEN_MASK 0x00000008
+#define SD4_EMMC_TOP_INTREN1_SD4_BLKEN_SHIFT 2
+#define SD4_EMMC_TOP_INTREN1_SD4_BLKEN_MASK 0x00000004
+#define SD4_EMMC_TOP_INTREN1_SD4_TXDONEEN_SHIFT 1
+#define SD4_EMMC_TOP_INTREN1_SD4_TXDONEEN_MASK 0x00000002
+#define SD4_EMMC_TOP_INTREN1_SD4_CMDDONEEN_SHIFT 0
+#define SD4_EMMC_TOP_INTREN1_SD4_CMDDONEEN_MASK 0x00000001
+
+#define SD4_EMMC_TOP_INTREN2_OFFSET 0x00000038
+#define SD4_EMMC_TOP_INTREN2_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_INTREN2_TYPE uint32_t
+#define SD4_EMMC_TOP_INTREN2_RESERVED_MASK 0xEC000000
+#define SD4_EMMC_TOP_INTREN2_TRESPERRSEN_SHIFT 28
+#define SD4_EMMC_TOP_INTREN2_TRESPERRSEN_MASK 0x10000000
+#define SD4_EMMC_TOP_INTREN2_ADMASIGEN_SHIFT 25
+#define SD4_EMMC_TOP_INTREN2_ADMASIGEN_MASK 0x02000000
+#define SD4_EMMC_TOP_INTREN2_CMDSIGEN_SHIFT 24
+#define SD4_EMMC_TOP_INTREN2_CMDSIGEN_MASK 0x01000000
+#define SD4_EMMC_TOP_INTREN2_ILIMSIGEN_SHIFT 23
+#define SD4_EMMC_TOP_INTREN2_ILIMSIGEN_MASK 0x00800000
+#define SD4_EMMC_TOP_INTREN2_DEBSIGEN_SHIFT 22
+#define SD4_EMMC_TOP_INTREN2_DEBSIGEN_MASK 0x00400000
+#define SD4_EMMC_TOP_INTREN2_DCRCSIGEN_SHIFT 21
+#define SD4_EMMC_TOP_INTREN2_DCRCSIGEN_MASK 0x00200000
+#define SD4_EMMC_TOP_INTREN2_DTOSIGEN_SHIFT 20
+#define SD4_EMMC_TOP_INTREN2_DTOSIGEN_MASK 0x00100000
+#define SD4_EMMC_TOP_INTREN2_CIDXSIGEN_SHIFT 19
+#define SD4_EMMC_TOP_INTREN2_CIDXSIGEN_MASK 0x00080000
+#define SD4_EMMC_TOP_INTREN2_CEBSIGEN_SHIFT 18
+#define SD4_EMMC_TOP_INTREN2_CEBSIGEN_MASK 0x00040000
+#define SD4_EMMC_TOP_INTREN2_CMDCRCSIGEN_SHIFT 17
+#define SD4_EMMC_TOP_INTREN2_CMDCRCSIGEN_MASK 0x00020000
+#define SD4_EMMC_TOP_INTREN2_CMDTOSIGEN_SHIFT 16
+#define SD4_EMMC_TOP_INTREN2_CMDTOSIGEN_MASK 0x00010000
+#define SD4_EMMC_TOP_INTREN2_FIXZERO_SHIFT 15
+#define SD4_EMMC_TOP_INTREN2_FIXZERO_MASK 0x00008000
+#define SD4_EMMC_TOP_INTREN2_BTIRQSEN_SHIFT 14
+#define SD4_EMMC_TOP_INTREN2_BTIRQSEN_MASK 0x00004000
+#define SD4_EMMC_TOP_INTREN2_BTACKRXSEN_SHIFT 13
+#define SD4_EMMC_TOP_INTREN2_BTACKRXSEN_MASK 0x00002000
+#define SD4_EMMC_TOP_INTREN2_RETUNE_EVENTSIGEN_SHIFT 12
+#define SD4_EMMC_TOP_INTREN2_RETUNE_EVENTSIGEN_MASK 0x00001000
+#define SD4_EMMC_TOP_INTREN2_INT_C_SIGEN_SHIFT 11
+#define SD4_EMMC_TOP_INTREN2_INT_C_SIGEN_MASK 0x00000800
+#define SD4_EMMC_TOP_INTREN2_INT_B_SIGEN_SHIFT 10
+#define SD4_EMMC_TOP_INTREN2_INT_B_SIGEN_MASK 0x00000400
+#define SD4_EMMC_TOP_INTREN2_INT_A_SIGEN_SHIFT 9
+#define SD4_EMMC_TOP_INTREN2_INT_A_SIGEN_MASK 0x00000200
+#define SD4_EMMC_TOP_INTREN2_CRDIRQEN_SHIFT 8
+#define SD4_EMMC_TOP_INTREN2_CRDIRQEN_MASK 0x00000100
+#define SD4_EMMC_TOP_INTREN2_CRDRVMEN_SHIFT 7
+#define SD4_EMMC_TOP_INTREN2_CRDRVMEN_MASK 0x00000080
+#define SD4_EMMC_TOP_INTREN2_CRDINSEN_SHIFT 6
+#define SD4_EMMC_TOP_INTREN2_CRDINSEN_MASK 0x00000040
+#define SD4_EMMC_TOP_INTREN2_BUFRRDYEN_SHIFT 5
+#define SD4_EMMC_TOP_INTREN2_BUFRRDYEN_MASK 0x00000020
+#define SD4_EMMC_TOP_INTREN2_BUFWRDYEN_SHIFT 4
+#define SD4_EMMC_TOP_INTREN2_BUFWRDYEN_MASK 0x00000010
+#define SD4_EMMC_TOP_INTREN2_DMAIRQEN_SHIFT 3
+#define SD4_EMMC_TOP_INTREN2_DMAIRQEN_MASK 0x00000008
+#define SD4_EMMC_TOP_INTREN2_BLKGAPEN_SHIFT 2
+#define SD4_EMMC_TOP_INTREN2_BLKGAPEN_MASK 0x00000004
+#define SD4_EMMC_TOP_INTREN2_TXDONE_SHIFT 1
+#define SD4_EMMC_TOP_INTREN2_TXDONE_MASK 0x00000002
+#define SD4_EMMC_TOP_INTREN2_CMDDONE_SHIFT 0
+#define SD4_EMMC_TOP_INTREN2_CMDDONE_MASK 0x00000001
+
+#define SD4_EMMC_TOP_INTREN2_SD4_OFFSET 0x00000038
+#define SD4_EMMC_TOP_INTREN2_SD4_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_INTREN2_SD4_TYPE uint32_t
+#define SD4_EMMC_TOP_INTREN2_SD4_RESERVED_MASK 0xF0006000
+#define SD4_EMMC_TOP_INTREN2_SD4_TRESPERRSEN_SHIFT 27
+#define SD4_EMMC_TOP_INTREN2_SD4_TRESPERRSEN_MASK 0x08000000
+#define SD4_EMMC_TOP_INTREN2_SD4_TUNERRSIGEN_SHIFT 26
+#define SD4_EMMC_TOP_INTREN2_SD4_TUNERRSIGEN_MASK 0x04000000
+#define SD4_EMMC_TOP_INTREN2_SD4_ADMASIGEN_SHIFT 25
+#define SD4_EMMC_TOP_INTREN2_SD4_ADMASIGEN_MASK 0x02000000
+#define SD4_EMMC_TOP_INTREN2_SD4_CMDSIGEN_SHIFT 24
+#define SD4_EMMC_TOP_INTREN2_SD4_CMDSIGEN_MASK 0x01000000
+#define SD4_EMMC_TOP_INTREN2_SD4_ILIMSIGEN_SHIFT 23
+#define SD4_EMMC_TOP_INTREN2_SD4_ILIMSIGEN_MASK 0x00800000
+#define SD4_EMMC_TOP_INTREN2_SD4_DEBSIGEN_SHIFT 22
+#define SD4_EMMC_TOP_INTREN2_SD4_DEBSIGEN_MASK 0x00400000
+#define SD4_EMMC_TOP_INTREN2_SD4_DCRCSIGEN_SHIFT 21
+#define SD4_EMMC_TOP_INTREN2_SD4_DCRCSIGEN_MASK 0x00200000
+#define SD4_EMMC_TOP_INTREN2_SD4_DTOSIGEN_SHIFT 20
+#define SD4_EMMC_TOP_INTREN2_SD4_DTOSIGEN_MASK 0x00100000
+#define SD4_EMMC_TOP_INTREN2_SD4_CIDXSIGEN_SHIFT 19
+#define SD4_EMMC_TOP_INTREN2_SD4_CIDXSIGEN_MASK 0x00080000
+#define SD4_EMMC_TOP_INTREN2_SD4_CEBSIGEN_SHIFT 18
+#define SD4_EMMC_TOP_INTREN2_SD4_CEBSIGEN_MASK 0x00040000
+#define SD4_EMMC_TOP_INTREN2_SD4_CMDCRCSIGEN_SHIFT 17
+#define SD4_EMMC_TOP_INTREN2_SD4_CMDCRCSIGEN_MASK 0x00020000
+#define SD4_EMMC_TOP_INTREN2_SD4_CMDTOSIGEN_SHIFT 16
+#define SD4_EMMC_TOP_INTREN2_SD4_CMDTOSIGEN_MASK 0x00010000
+#define SD4_EMMC_TOP_INTREN2_SD4_FIXZERO_SHIFT 15
+#define SD4_EMMC_TOP_INTREN2_SD4_FIXZERO_MASK 0x00008000
+#define SD4_EMMC_TOP_INTREN2_SD4_RETUNE_EVENTSIGEN_SHIFT 12
+#define SD4_EMMC_TOP_INTREN2_SD4_RETUNE_EVENTSIGEN_MASK 0x00001000
+#define SD4_EMMC_TOP_INTREN2_SD4_INT_C_SIGEN_SHIFT 11
+#define SD4_EMMC_TOP_INTREN2_SD4_INT_C_SIGEN_MASK 0x00000800
+#define SD4_EMMC_TOP_INTREN2_SD4_INT_B_SIGEN_SHIFT 10
+#define SD4_EMMC_TOP_INTREN2_SD4_INT_B_SIGEN_MASK 0x00000400
+#define SD4_EMMC_TOP_INTREN2_SD4_INT_A_SIGEN_SHIFT 9
+#define SD4_EMMC_TOP_INTREN2_SD4_INT_A_SIGEN_MASK 0x00000200
+#define SD4_EMMC_TOP_INTREN2_SD4_CRDIRQEN_SHIFT 8
+#define SD4_EMMC_TOP_INTREN2_SD4_CRDIRQEN_MASK 0x00000100
+#define SD4_EMMC_TOP_INTREN2_SD4_CRDRVMEN_SHIFT 7
+#define SD4_EMMC_TOP_INTREN2_SD4_CRDRVMEN_MASK 0x00000080
+#define SD4_EMMC_TOP_INTREN2_SD4_CRDINSEN_SHIFT 6
+#define SD4_EMMC_TOP_INTREN2_SD4_CRDINSEN_MASK 0x00000040
+#define SD4_EMMC_TOP_INTREN2_SD4_BUFRRDYEN_SHIFT 5
+#define SD4_EMMC_TOP_INTREN2_SD4_BUFRRDYEN_MASK 0x00000020
+#define SD4_EMMC_TOP_INTREN2_SD4_BUFWRDYEN_SHIFT 4
+#define SD4_EMMC_TOP_INTREN2_SD4_BUFWRDYEN_MASK 0x00000010
+#define SD4_EMMC_TOP_INTREN2_SD4_DMAIRQEN_SHIFT 3
+#define SD4_EMMC_TOP_INTREN2_SD4_DMAIRQEN_MASK 0x00000008
+#define SD4_EMMC_TOP_INTREN2_SD4_BLKGAPEN_SHIFT 2
+#define SD4_EMMC_TOP_INTREN2_SD4_BLKGAPEN_MASK 0x00000004
+#define SD4_EMMC_TOP_INTREN2_SD4_TXDONE_SHIFT 1
+#define SD4_EMMC_TOP_INTREN2_SD4_TXDONE_MASK 0x00000002
+#define SD4_EMMC_TOP_INTREN2_SD4_CMDDONE_SHIFT 0
+#define SD4_EMMC_TOP_INTREN2_SD4_CMDDONE_MASK 0x00000001
+
+#define SD4_EMMC_TOP_ERRSTAT_OFFSET 0x0000003C
+#define SD4_EMMC_TOP_ERRSTAT_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_ERRSTAT_TYPE uint32_t
+#define SD4_EMMC_TOP_ERRSTAT_RESERVED_MASK 0x3F00FF60
+#define SD4_EMMC_TOP_ERRSTAT_PRESETEN_SHIFT 31
+#define SD4_EMMC_TOP_ERRSTAT_PRESETEN_MASK 0x80000000
+#define SD4_EMMC_TOP_ERRSTAT_ASYNC_INTREN_SHIFT 30
+#define SD4_EMMC_TOP_ERRSTAT_ASYNC_INTREN_MASK 0x40000000
+#define SD4_EMMC_TOP_ERRSTAT_SAMPLECLOCKSEL_SHIFT 23
+#define SD4_EMMC_TOP_ERRSTAT_SAMPLECLOCKSEL_MASK 0x00800000
+#define SD4_EMMC_TOP_ERRSTAT_EXECTUNE_SHIFT 22
+#define SD4_EMMC_TOP_ERRSTAT_EXECTUNE_MASK 0x00400000
+#define SD4_EMMC_TOP_ERRSTAT_DRVSTRESEL_SHIFT 20
+#define SD4_EMMC_TOP_ERRSTAT_DRVSTRESEL_MASK 0x00300000
+#define SD4_EMMC_TOP_ERRSTAT_EN1P8V_SHIFT 19
+#define SD4_EMMC_TOP_ERRSTAT_EN1P8V_MASK 0x00080000
+#define SD4_EMMC_TOP_ERRSTAT_UHSMODESEL_SHIFT 16
+#define SD4_EMMC_TOP_ERRSTAT_UHSMODESEL_MASK 0x00070000
+#define SD4_EMMC_TOP_ERRSTAT_NOCMD_SHIFT 7
+#define SD4_EMMC_TOP_ERRSTAT_NOCMD_MASK 0x00000080
+#define SD4_EMMC_TOP_ERRSTAT_CMDIDXERR_SHIFT 4
+#define SD4_EMMC_TOP_ERRSTAT_CMDIDXERR_MASK 0x00000010
+#define SD4_EMMC_TOP_ERRSTAT_CMDENDERR_SHIFT 3
+#define SD4_EMMC_TOP_ERRSTAT_CMDENDERR_MASK 0x00000008
+#define SD4_EMMC_TOP_ERRSTAT_CMDCRCERR_SHIFT 2
+#define SD4_EMMC_TOP_ERRSTAT_CMDCRCERR_MASK 0x00000004
+#define SD4_EMMC_TOP_ERRSTAT_CMDTOERR_SHIFT 1
+#define SD4_EMMC_TOP_ERRSTAT_CMDTOERR_MASK 0x00000002
+#define SD4_EMMC_TOP_ERRSTAT_CMDNOEXEC_SHIFT 0
+#define SD4_EMMC_TOP_ERRSTAT_CMDNOEXEC_MASK 0x00000001
+
+#define SD4_EMMC_TOP_ERRSTAT_SD4_OFFSET 0x0000003C
+#define SD4_EMMC_TOP_ERRSTAT_SD4_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_ERRSTAT_SD4_TYPE uint32_t
+#define SD4_EMMC_TOP_ERRSTAT_SD4_RESERVED_MASK 0x0E00FF40
+#define SD4_EMMC_TOP_ERRSTAT_SD4_PRESETEN_SHIFT 31
+#define SD4_EMMC_TOP_ERRSTAT_SD4_PRESETEN_MASK 0x80000000
+#define SD4_EMMC_TOP_ERRSTAT_SD4_ASYNC_INTREN_SHIFT 30
+#define SD4_EMMC_TOP_ERRSTAT_SD4_ASYNC_INTREN_MASK 0x40000000
+#define SD4_EMMC_TOP_ERRSTAT_SD4_ADDR64_SHIFT 29
+#define SD4_EMMC_TOP_ERRSTAT_SD4_ADDR64_MASK 0x20000000
+#define SD4_EMMC_TOP_ERRSTAT_SD4_HOSTVER4_00_SHIFT 28
+#define SD4_EMMC_TOP_ERRSTAT_SD4_HOSTVER4_00_MASK 0x10000000
+#define SD4_EMMC_TOP_ERRSTAT_SD4_UHS2INTFEN_SHIFT 24
+#define SD4_EMMC_TOP_ERRSTAT_SD4_UHS2INTFEN_MASK 0x01000000
+#define SD4_EMMC_TOP_ERRSTAT_SD4_SAMPLECLOCKSEL_SHIFT 23
+#define SD4_EMMC_TOP_ERRSTAT_SD4_SAMPLECLOCKSEL_MASK 0x00800000
+#define SD4_EMMC_TOP_ERRSTAT_SD4_EXECTUNE_SHIFT 22
+#define SD4_EMMC_TOP_ERRSTAT_SD4_EXECTUNE_MASK 0x00400000
+#define SD4_EMMC_TOP_ERRSTAT_SD4_DRVSTRESEL_SHIFT 20
+#define SD4_EMMC_TOP_ERRSTAT_SD4_DRVSTRESEL_MASK 0x00300000
+#define SD4_EMMC_TOP_ERRSTAT_SD4_EN1P8V_SHIFT 19
+#define SD4_EMMC_TOP_ERRSTAT_SD4_EN1P8V_MASK 0x00080000
+#define SD4_EMMC_TOP_ERRSTAT_SD4_UHSMODESEL_SHIFT 16
+#define SD4_EMMC_TOP_ERRSTAT_SD4_UHSMODESEL_MASK 0x00070000
+#define SD4_EMMC_TOP_ERRSTAT_SD4_NOCMD_SHIFT 7
+#define SD4_EMMC_TOP_ERRSTAT_SD4_NOCMD_MASK 0x00000080
+#define SD4_EMMC_TOP_ERRSTAT_SD4_CMDRESPERR_SHIFT 5
+#define SD4_EMMC_TOP_ERRSTAT_SD4_CMDRESPERR_MASK 0x00000020
+#define SD4_EMMC_TOP_ERRSTAT_SD4_CMDIDXERR_SHIFT 4
+#define SD4_EMMC_TOP_ERRSTAT_SD4_CMDIDXERR_MASK 0x00000010
+#define SD4_EMMC_TOP_ERRSTAT_SD4_CMDENDERR_SHIFT 3
+#define SD4_EMMC_TOP_ERRSTAT_SD4_CMDENDERR_MASK 0x00000008
+#define SD4_EMMC_TOP_ERRSTAT_SD4_CMDCRCERR_SHIFT 2
+#define SD4_EMMC_TOP_ERRSTAT_SD4_CMDCRCERR_MASK 0x00000004
+#define SD4_EMMC_TOP_ERRSTAT_SD4_CMDTOERR_SHIFT 1
+#define SD4_EMMC_TOP_ERRSTAT_SD4_CMDTOERR_MASK 0x00000002
+#define SD4_EMMC_TOP_ERRSTAT_SD4_CMDNOEXEC_SHIFT 0
+#define SD4_EMMC_TOP_ERRSTAT_SD4_CMDNOEXEC_MASK 0x00000001
+
+#define SD4_EMMC_TOP_CAPABILITIES1_OFFSET 0x00000040
+#define SD4_EMMC_TOP_CAPABILITIES1_DEFAULT 0x17EFD0B0
+#define SD4_EMMC_TOP_CAPABILITIES1_TYPE uint32_t
+#define SD4_EMMC_TOP_CAPABILITIES1_RESERVED_MASK 0x08100040
+#define SD4_EMMC_TOP_CAPABILITIES1_SLOTTYPE_SHIFT 30
+#define SD4_EMMC_TOP_CAPABILITIES1_SLOTTYPE_MASK 0xC0000000
+#define SD4_EMMC_TOP_CAPABILITIES1_ASYNCHIRQ_SHIFT 29
+#define SD4_EMMC_TOP_CAPABILITIES1_ASYNCHIRQ_MASK 0x20000000
+#define SD4_EMMC_TOP_CAPABILITIES1_SYSBUS64_SHIFT 28
+#define SD4_EMMC_TOP_CAPABILITIES1_SYSBUS64_MASK 0x10000000
+#define SD4_EMMC_TOP_CAPABILITIES1_V18_SHIFT 26
+#define SD4_EMMC_TOP_CAPABILITIES1_V18_MASK 0x04000000
+#define SD4_EMMC_TOP_CAPABILITIES1_V3_SHIFT 25
+#define SD4_EMMC_TOP_CAPABILITIES1_V3_MASK 0x02000000
+#define SD4_EMMC_TOP_CAPABILITIES1_V33_SHIFT 24
+#define SD4_EMMC_TOP_CAPABILITIES1_V33_MASK 0x01000000
+#define SD4_EMMC_TOP_CAPABILITIES1_SUPRSM_SHIFT 23
+#define SD4_EMMC_TOP_CAPABILITIES1_SUPRSM_MASK 0x00800000
+#define SD4_EMMC_TOP_CAPABILITIES1_SDMA_SHIFT 22
+#define SD4_EMMC_TOP_CAPABILITIES1_SDMA_MASK 0x00400000
+#define SD4_EMMC_TOP_CAPABILITIES1_HSPEED_SHIFT 21
+#define SD4_EMMC_TOP_CAPABILITIES1_HSPEED_MASK 0x00200000
+#define SD4_EMMC_TOP_CAPABILITIES1_ADMA2_SHIFT 19
+#define SD4_EMMC_TOP_CAPABILITIES1_ADMA2_MASK 0x00080000
+#define SD4_EMMC_TOP_CAPABILITIES1_EXTBUSMED_SHIFT 18
+#define SD4_EMMC_TOP_CAPABILITIES1_EXTBUSMED_MASK 0x00040000
+#define SD4_EMMC_TOP_CAPABILITIES1_MAXBLK_SHIFT 16
+#define SD4_EMMC_TOP_CAPABILITIES1_MAXBLK_MASK 0x00030000
+#define SD4_EMMC_TOP_CAPABILITIES1_BCLK_SHIFT 8
+#define SD4_EMMC_TOP_CAPABILITIES1_BCLK_MASK 0x0000FF00
+#define SD4_EMMC_TOP_CAPABILITIES1_TOUT_SHIFT 7
+#define SD4_EMMC_TOP_CAPABILITIES1_TOUT_MASK 0x00000080
+#define SD4_EMMC_TOP_CAPABILITIES1_TOUTFREQ_SHIFT 0
+#define SD4_EMMC_TOP_CAPABILITIES1_TOUTFREQ_MASK 0x0000003F
+
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_OFFSET 0x00000040
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_DEFAULT 0x10E934B4
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_TYPE uint32_t
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_RESERVED_MASK 0x08100040
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_SLOTTYPE_SHIFT 30
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_SLOTTYPE_MASK 0xC0000000
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_ASYNCHIRQ_SHIFT 29
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_ASYNCHIRQ_MASK 0x20000000
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_SYSBUS64_SHIFT 28
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_SYSBUS64_MASK 0x10000000
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_V18_SHIFT 26
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_V18_MASK 0x04000000
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_V3_SHIFT 25
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_V3_MASK 0x02000000
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_V33_SHIFT 24
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_V33_MASK 0x01000000
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_SUPRSM_SHIFT 23
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_SUPRSM_MASK 0x00800000
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_SDMA_SHIFT 22
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_SDMA_MASK 0x00400000
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_HSPEED_SHIFT 21
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_HSPEED_MASK 0x00200000
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_ADMA2_SHIFT 19
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_ADMA2_MASK 0x00080000
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_EXTBUSMED_SHIFT 18
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_EXTBUSMED_MASK 0x00040000
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_MAXBLK_SHIFT 16
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_MAXBLK_MASK 0x00030000
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_BCLK_SHIFT 8
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_BCLK_MASK 0x0000FF00
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_TOUT_SHIFT 7
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_TOUT_MASK 0x00000080
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_TOUTFREQ_SHIFT 0
+#define SD4_EMMC_TOP_CAPABILITIES1_SD4_TOUTFREQ_MASK 0x0000003F
+
+#define SD4_EMMC_TOP_CAPABILITIES2_OFFSET 0x00000044
+#define SD4_EMMC_TOP_CAPABILITIES2_DEFAULT 0x03002177
+#define SD4_EMMC_TOP_CAPABILITIES2_TYPE uint32_t
+#define SD4_EMMC_TOP_CAPABILITIES2_RESERVED_MASK 0xFC001088
+#define SD4_EMMC_TOP_CAPABILITIES2_SPIBLOCKMODE_SHIFT 25
+#define SD4_EMMC_TOP_CAPABILITIES2_SPIBLOCKMODE_MASK 0x02000000
+#define SD4_EMMC_TOP_CAPABILITIES2_SPIMODE_CAP_SHIFT 24
+#define SD4_EMMC_TOP_CAPABILITIES2_SPIMODE_CAP_MASK 0x01000000
+#define SD4_EMMC_TOP_CAPABILITIES2_CLOCKMULT_SHIFT 16
+#define SD4_EMMC_TOP_CAPABILITIES2_CLOCKMULT_MASK 0x00FF0000
+#define SD4_EMMC_TOP_CAPABILITIES2_RETUNE_MODE_SHIFT 14
+#define SD4_EMMC_TOP_CAPABILITIES2_RETUNE_MODE_MASK 0x0000C000
+#define SD4_EMMC_TOP_CAPABILITIES2_USETUNE_SDR50_SHIFT 13
+#define SD4_EMMC_TOP_CAPABILITIES2_USETUNE_SDR50_MASK 0x00002000
+#define SD4_EMMC_TOP_CAPABILITIES2_TMRCNT_RETUNE_SHIFT 8
+#define SD4_EMMC_TOP_CAPABILITIES2_TMRCNT_RETUNE_MASK 0x00000F00
+#define SD4_EMMC_TOP_CAPABILITIES2_DRVR_TYPED_SHIFT 6
+#define SD4_EMMC_TOP_CAPABILITIES2_DRVR_TYPED_MASK 0x00000040
+#define SD4_EMMC_TOP_CAPABILITIES2_DRVR_TYPEC_SHIFT 5
+#define SD4_EMMC_TOP_CAPABILITIES2_DRVR_TYPEC_MASK 0x00000020
+#define SD4_EMMC_TOP_CAPABILITIES2_DRVR_TYPEA_SHIFT 4
+#define SD4_EMMC_TOP_CAPABILITIES2_DRVR_TYPEA_MASK 0x00000010
+#define SD4_EMMC_TOP_CAPABILITIES2_DDR50_SHIFT 2
+#define SD4_EMMC_TOP_CAPABILITIES2_DDR50_MASK 0x00000004
+#define SD4_EMMC_TOP_CAPABILITIES2_SDR104_SHIFT 1
+#define SD4_EMMC_TOP_CAPABILITIES2_SDR104_MASK 0x00000002
+#define SD4_EMMC_TOP_CAPABILITIES2_SDR50_SHIFT 0
+#define SD4_EMMC_TOP_CAPABILITIES2_SDR50_MASK 0x00000001
+
+#define SD4_EMMC_TOP_CAPABILITIES2_SD4_OFFSET 0x00000044
+#define SD4_EMMC_TOP_CAPABILITIES2_SD4_DEFAULT 0x10000064
+#define SD4_EMMC_TOP_CAPABILITIES2_SD4_TYPE uint32_t
+#define SD4_EMMC_TOP_CAPABILITIES2_SD4_RESERVED_MASK 0xE7001080
+#define SD4_EMMC_TOP_CAPABILITIES2_SD4_VDD2_18_SHIFT 28
+#define SD4_EMMC_TOP_CAPABILITIES2_SD4_VDD2_18_MASK 0x10000000
+#define SD4_EMMC_TOP_CAPABILITIES2_SD4_ADMA3_SHIFT 27
+#define SD4_EMMC_TOP_CAPABILITIES2_SD4_ADMA3_MASK 0x08000000
+#define SD4_EMMC_TOP_CAPABILITIES2_SD4_CLOCKMULT_SHIFT 16
+#define SD4_EMMC_TOP_CAPABILITIES2_SD4_CLOCKMULT_MASK 0x00FF0000
+#define SD4_EMMC_TOP_CAPABILITIES2_SD4_RETUNE_MODE_SHIFT 14
+#define SD4_EMMC_TOP_CAPABILITIES2_SD4_RETUNE_MODE_MASK 0x0000C000
+#define SD4_EMMC_TOP_CAPABILITIES2_SD4_USETUNE_SDR50_SHIFT 13
+#define SD4_EMMC_TOP_CAPABILITIES2_SD4_USETUNE_SDR50_MASK 0x00002000
+#define SD4_EMMC_TOP_CAPABILITIES2_SD4_TMRCNT_RETUNE_SHIFT 8
+#define SD4_EMMC_TOP_CAPABILITIES2_SD4_TMRCNT_RETUNE_MASK 0x00000F00
+#define SD4_EMMC_TOP_CAPABILITIES2_SD4_DRVR_TYPED_SHIFT 6
+#define SD4_EMMC_TOP_CAPABILITIES2_SD4_DRVR_TYPED_MASK 0x00000040
+#define SD4_EMMC_TOP_CAPABILITIES2_SD4_DRVR_TYPEC_SHIFT 5
+#define SD4_EMMC_TOP_CAPABILITIES2_SD4_DRVR_TYPEC_MASK 0x00000020
+#define SD4_EMMC_TOP_CAPABILITIES2_SD4_DRVR_TYPEA_SHIFT 4
+#define SD4_EMMC_TOP_CAPABILITIES2_SD4_DRVR_TYPEA_MASK 0x00000010
+#define SD4_EMMC_TOP_CAPABILITIES2_SD4_UHS_II_SHIFT 3
+#define SD4_EMMC_TOP_CAPABILITIES2_SD4_UHS_II_MASK 0x00000008
+#define SD4_EMMC_TOP_CAPABILITIES2_SD4_DDR50_SHIFT 2
+#define SD4_EMMC_TOP_CAPABILITIES2_SD4_DDR50_MASK 0x00000004
+#define SD4_EMMC_TOP_CAPABILITIES2_SD4_SDR104_SHIFT 1
+#define SD4_EMMC_TOP_CAPABILITIES2_SD4_SDR104_MASK 0x00000002
+#define SD4_EMMC_TOP_CAPABILITIES2_SD4_SDR50_SHIFT 0
+#define SD4_EMMC_TOP_CAPABILITIES2_SD4_SDR50_MASK 0x00000001
+
+#define SD4_EMMC_TOP_MAX_A1_OFFSET 0x00000048
+#define SD4_EMMC_TOP_MAX_A1_DEFAULT 0x00000001
+#define SD4_EMMC_TOP_MAX_A1_TYPE uint32_t
+#define SD4_EMMC_TOP_MAX_A1_RESERVED_MASK 0xFF000000
+#define SD4_EMMC_TOP_MAX_A1_MAXA18_SHIFT 16
+#define SD4_EMMC_TOP_MAX_A1_MAXA18_MASK 0x00FF0000
+#define SD4_EMMC_TOP_MAX_A1_MAXA30_SHIFT 8
+#define SD4_EMMC_TOP_MAX_A1_MAXA30_MASK 0x0000FF00
+#define SD4_EMMC_TOP_MAX_A1_MAXA33_SHIFT 0
+#define SD4_EMMC_TOP_MAX_A1_MAXA33_MASK 0x000000FF
+
+#define SD4_EMMC_TOP_MAX_A2_OFFSET 0x0000004C
+#define SD4_EMMC_TOP_MAX_A2_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_MAX_A2_TYPE uint32_t
+#define SD4_EMMC_TOP_MAX_A2_RESERVED_MASK 0xFFFFFFFF
+
+#define SD4_EMMC_TOP_MAX_A2_SD4_OFFSET 0x0000004C
+#define SD4_EMMC_TOP_MAX_A2_SD4_DEFAULT 0x00000001
+#define SD4_EMMC_TOP_MAX_A2_SD4_TYPE uint32_t
+#define SD4_EMMC_TOP_MAX_A2_SD4_RESERVED_MASK 0xFFFFFF00
+#define SD4_EMMC_TOP_MAX_A2_SD4_MAXAVDD2_SHIFT 0
+#define SD4_EMMC_TOP_MAX_A2_SD4_MAXAVDD2_MASK 0x000000FF
+
+#define SD4_EMMC_TOP_CMDENTSTAT_OFFSET 0x00000050
+#define SD4_EMMC_TOP_CMDENTSTAT_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_CMDENTSTAT_TYPE uint32_t
+#define SD4_EMMC_TOP_CMDENTSTAT_RESERVED_MASK 0x2C00FF60
+#define SD4_EMMC_TOP_CMDENTSTAT_VSES_SHIFT 30
+#define SD4_EMMC_TOP_CMDENTSTAT_VSES_MASK 0xC0000000
+#define SD4_EMMC_TOP_CMDENTSTAT_TRERR_SHIFT 28
+#define SD4_EMMC_TOP_CMDENTSTAT_TRERR_MASK 0x10000000
+#define SD4_EMMC_TOP_CMDENTSTAT_ADMAERR_SHIFT 25
+#define SD4_EMMC_TOP_CMDENTSTAT_ADMAERR_MASK 0x02000000
+#define SD4_EMMC_TOP_CMDENTSTAT_ACMDERR_SHIFT 24
+#define SD4_EMMC_TOP_CMDENTSTAT_ACMDERR_MASK 0x01000000
+#define SD4_EMMC_TOP_CMDENTSTAT_ILERR_SHIFT 23
+#define SD4_EMMC_TOP_CMDENTSTAT_ILERR_MASK 0x00800000
+#define SD4_EMMC_TOP_CMDENTSTAT_DENDERR_SHIFT 22
+#define SD4_EMMC_TOP_CMDENTSTAT_DENDERR_MASK 0x00400000
+#define SD4_EMMC_TOP_CMDENTSTAT_DCRCERR_SHIFT 21
+#define SD4_EMMC_TOP_CMDENTSTAT_DCRCERR_MASK 0x00200000
+#define SD4_EMMC_TOP_CMDENTSTAT_DTOUTERR_SHIFT 20
+#define SD4_EMMC_TOP_CMDENTSTAT_DTOUTERR_MASK 0x00100000
+#define SD4_EMMC_TOP_CMDENTSTAT_CIDXERR_SHIFT 19
+#define SD4_EMMC_TOP_CMDENTSTAT_CIDXERR_MASK 0x00080000
+#define SD4_EMMC_TOP_CMDENTSTAT_CENDERR_SHIFT 18
+#define SD4_EMMC_TOP_CMDENTSTAT_CENDERR_MASK 0x00040000
+#define SD4_EMMC_TOP_CMDENTSTAT_CCRCERR_SHIFT 17
+#define SD4_EMMC_TOP_CMDENTSTAT_CCRCERR_MASK 0x00020000
+#define SD4_EMMC_TOP_CMDENTSTAT_CTOUTERR_SHIFT 16
+#define SD4_EMMC_TOP_CMDENTSTAT_CTOUTERR_MASK 0x00010000
+#define SD4_EMMC_TOP_CMDENTSTAT_NOFRCENT_SHIFT 7
+#define SD4_EMMC_TOP_CMDENTSTAT_NOFRCENT_MASK 0x00000080
+#define SD4_EMMC_TOP_CMDENTSTAT_IDXERR_SHIFT 4
+#define SD4_EMMC_TOP_CMDENTSTAT_IDXERR_MASK 0x00000010
+#define SD4_EMMC_TOP_CMDENTSTAT_EBITERR_SHIFT 3
+#define SD4_EMMC_TOP_CMDENTSTAT_EBITERR_MASK 0x00000008
+#define SD4_EMMC_TOP_CMDENTSTAT_CRCERR_SHIFT 2
+#define SD4_EMMC_TOP_CMDENTSTAT_CRCERR_MASK 0x00000004
+#define SD4_EMMC_TOP_CMDENTSTAT_TOUTERR_SHIFT 1
+#define SD4_EMMC_TOP_CMDENTSTAT_TOUTERR_MASK 0x00000002
+#define SD4_EMMC_TOP_CMDENTSTAT_AUTONOEX_SHIFT 0
+#define SD4_EMMC_TOP_CMDENTSTAT_AUTONOEX_MASK 0x00000001
+
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_OFFSET 0x00000050
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_TYPE uint32_t
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_RESERVED_MASK 0x0000FF40
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_VSES_SHIFT 28
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_VSES_MASK 0xF0000000
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_TRESPERR_SHIFT 27
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_TRESPERR_MASK 0x08000000
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_TUNERR_SHIFT 26
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_TUNERR_MASK 0x04000000
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_ADMAERR_SHIFT 25
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_ADMAERR_MASK 0x02000000
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_ACMDERR_SHIFT 24
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_ACMDERR_MASK 0x01000000
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_ILERR_SHIFT 23
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_ILERR_MASK 0x00800000
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_DENDERR_SHIFT 22
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_DENDERR_MASK 0x00400000
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_DCRCERR_SHIFT 21
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_DCRCERR_MASK 0x00200000
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_DTOUTERR_SHIFT 20
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_DTOUTERR_MASK 0x00100000
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_CIDXERR_SHIFT 19
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_CIDXERR_MASK 0x00080000
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_CENDERR_SHIFT 18
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_CENDERR_MASK 0x00040000
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_CCRCERR_SHIFT 17
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_CCRCERR_MASK 0x00020000
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_CTOUTERR_SHIFT 16
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_CTOUTERR_MASK 0x00010000
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_NOFRCENT_SHIFT 7
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_NOFRCENT_MASK 0x00000080
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_RESPERR_SHIFT 5
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_RESPERR_MASK 0x00000020
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_IDXERR_SHIFT 4
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_IDXERR_MASK 0x00000010
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_EBITERR_SHIFT 3
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_EBITERR_MASK 0x00000008
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_CRCERR_SHIFT 2
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_CRCERR_MASK 0x00000004
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_TOUTERR_SHIFT 1
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_TOUTERR_MASK 0x00000002
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_AUTONOEX_SHIFT 0
+#define SD4_EMMC_TOP_CMDENTSTAT_SD4_AUTONOEX_MASK 0x00000001
+
+#define SD4_EMMC_TOP_ADMAERR_OFFSET 0x00000054
+#define SD4_EMMC_TOP_ADMAERR_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_ADMAERR_TYPE uint32_t
+#define SD4_EMMC_TOP_ADMAERR_RESERVED_MASK 0xFFFFFFF8
+#define SD4_EMMC_TOP_ADMAERR_ADMALERR_SHIFT 2
+#define SD4_EMMC_TOP_ADMAERR_ADMALERR_MASK 0x00000004
+#define SD4_EMMC_TOP_ADMAERR_ADMAERR_SHIFT 0
+#define SD4_EMMC_TOP_ADMAERR_ADMAERR_MASK 0x00000003
+
+#define SD4_EMMC_TOP_ADMAADDR0_OFFSET 0x00000058
+#define SD4_EMMC_TOP_ADMAADDR0_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_ADMAADDR0_TYPE uint32_t
+#define SD4_EMMC_TOP_ADMAADDR0_RESERVED_MASK 0x00000000
+#define SD4_EMMC_TOP_ADMAADDR0_ADMAADDR0_SHIFT 0
+#define SD4_EMMC_TOP_ADMAADDR0_ADMAADDR0_MASK 0xFFFFFFFF
+
+#define SD4_EMMC_TOP_ADMAADDR1_OFFSET 0x0000005C
+#define SD4_EMMC_TOP_ADMAADDR1_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_ADMAADDR1_TYPE uint32_t
+#define SD4_EMMC_TOP_ADMAADDR1_RESERVED_MASK 0x00000000
+#define SD4_EMMC_TOP_ADMAADDR1_ADMAADDR1_SHIFT 0
+#define SD4_EMMC_TOP_ADMAADDR1_ADMAADDR1_MASK 0xFFFFFFFF
+
+#define SD4_EMMC_TOP_PRESETVAL1_OFFSET 0x00000060
+#define SD4_EMMC_TOP_PRESETVAL1_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_PRESETVAL1_TYPE uint32_t
+#define SD4_EMMC_TOP_PRESETVAL1_RESERVED_MASK 0x38003800
+#define SD4_EMMC_TOP_PRESETVAL1_DRVS_SEL_DFS_SHIFT 30
+#define SD4_EMMC_TOP_PRESETVAL1_DRVS_SEL_DFS_MASK 0xC0000000
+#define SD4_EMMC_TOP_PRESETVAL1_CLKGENSEL_DFS_SHIFT 26
+#define SD4_EMMC_TOP_PRESETVAL1_CLKGENSEL_DFS_MASK 0x04000000
+#define SD4_EMMC_TOP_PRESETVAL1_FREQ_SEL_DFS_SHIFT 16
+#define SD4_EMMC_TOP_PRESETVAL1_FREQ_SEL_DFS_MASK 0x03FF0000
+#define SD4_EMMC_TOP_PRESETVAL1_DRVS_SEL_INIT_SHIFT 14
+#define SD4_EMMC_TOP_PRESETVAL1_DRVS_SEL_INIT_MASK 0x0000C000
+#define SD4_EMMC_TOP_PRESETVAL1_CLKGENSEL_INIT_SHIFT 10
+#define SD4_EMMC_TOP_PRESETVAL1_CLKGENSEL_INIT_MASK 0x00000400
+#define SD4_EMMC_TOP_PRESETVAL1_FREQ_SEL_INIT_SHIFT 0
+#define SD4_EMMC_TOP_PRESETVAL1_FREQ_SEL_INIT_MASK 0x000003FF
+
+#define SD4_EMMC_TOP_PRESETVAL2_OFFSET 0x00000064
+#define SD4_EMMC_TOP_PRESETVAL2_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_PRESETVAL2_TYPE uint32_t
+#define SD4_EMMC_TOP_PRESETVAL2_RESERVED_MASK 0x38003800
+#define SD4_EMMC_TOP_PRESETVAL2_DRVS_SEL_SDR12_SHIFT 30
+#define SD4_EMMC_TOP_PRESETVAL2_DRVS_SEL_SDR12_MASK 0xC0000000
+#define SD4_EMMC_TOP_PRESETVAL2_CLKGENSEL_SDR12_SHIFT 26
+#define SD4_EMMC_TOP_PRESETVAL2_CLKGENSEL_SDR12_MASK 0x04000000
+#define SD4_EMMC_TOP_PRESETVAL2_FREQ_SEL_SDR12_SHIFT 16
+#define SD4_EMMC_TOP_PRESETVAL2_FREQ_SEL_SDR12_MASK 0x03FF0000
+#define SD4_EMMC_TOP_PRESETVAL2_DRVS_SEL_HS_SHIFT 14
+#define SD4_EMMC_TOP_PRESETVAL2_DRVS_SEL_HS_MASK 0x0000C000
+#define SD4_EMMC_TOP_PRESETVAL2_CLKGENSEL_HS_SHIFT 10
+#define SD4_EMMC_TOP_PRESETVAL2_CLKGENSEL_HS_MASK 0x00000400
+#define SD4_EMMC_TOP_PRESETVAL2_FREQ_SEL_HS_SHIFT 0
+#define SD4_EMMC_TOP_PRESETVAL2_FREQ_SEL_HS_MASK 0x000003FF
+
+#define SD4_EMMC_TOP_PRESETVAL3_OFFSET 0x00000068
+#define SD4_EMMC_TOP_PRESETVAL3_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_PRESETVAL3_TYPE uint32_t
+#define SD4_EMMC_TOP_PRESETVAL3_RESERVED_MASK 0x38003800
+#define SD4_EMMC_TOP_PRESETVAL3_DRVS_SEL_SDR50_SHIFT 30
+#define SD4_EMMC_TOP_PRESETVAL3_DRVS_SEL_SDR50_MASK 0xC0000000
+#define SD4_EMMC_TOP_PRESETVAL3_CLKGENSEL_SDR50_SHIFT 26
+#define SD4_EMMC_TOP_PRESETVAL3_CLKGENSEL_SDR50_MASK 0x04000000
+#define SD4_EMMC_TOP_PRESETVAL3_FREQ_SEL_SDR50_SHIFT 16
+#define SD4_EMMC_TOP_PRESETVAL3_FREQ_SEL_SDR50_MASK 0x03FF0000
+#define SD4_EMMC_TOP_PRESETVAL3_DRVS_SEL_SDR25_SHIFT 14
+#define SD4_EMMC_TOP_PRESETVAL3_DRVS_SEL_SDR25_MASK 0x0000C000
+#define SD4_EMMC_TOP_PRESETVAL3_CLKGENSEL_SDR25_SHIFT 10
+#define SD4_EMMC_TOP_PRESETVAL3_CLKGENSEL_SDR25_MASK 0x00000400
+#define SD4_EMMC_TOP_PRESETVAL3_FREQ_SEL_SDR25_SHIFT 0
+#define SD4_EMMC_TOP_PRESETVAL3_FREQ_SEL_SDR25_MASK 0x000003FF
+
+#define SD4_EMMC_TOP_PRESETVAL4_OFFSET 0x0000006C
+#define SD4_EMMC_TOP_PRESETVAL4_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_PRESETVAL4_TYPE uint32_t
+#define SD4_EMMC_TOP_PRESETVAL4_RESERVED_MASK 0x38003800
+#define SD4_EMMC_TOP_PRESETVAL4_DRVS_SEL_DDR50_SHIFT 30
+#define SD4_EMMC_TOP_PRESETVAL4_DRVS_SEL_DDR50_MASK 0xC0000000
+#define SD4_EMMC_TOP_PRESETVAL4_CLKGENSEL_DDR50_SHIFT 26
+#define SD4_EMMC_TOP_PRESETVAL4_CLKGENSEL_DDR50_MASK 0x04000000
+#define SD4_EMMC_TOP_PRESETVAL4_FREQ_SEL_DDR50_SHIFT 16
+#define SD4_EMMC_TOP_PRESETVAL4_FREQ_SEL_DDR50_MASK 0x03FF0000
+#define SD4_EMMC_TOP_PRESETVAL4_DRVS_SEL_SDR104_SHIFT 14
+#define SD4_EMMC_TOP_PRESETVAL4_DRVS_SEL_SDR104_MASK 0x0000C000
+#define SD4_EMMC_TOP_PRESETVAL4_CLKGENSEL_SDR104_SHIFT 10
+#define SD4_EMMC_TOP_PRESETVAL4_CLKGENSEL_SDR104_MASK 0x00000400
+#define SD4_EMMC_TOP_PRESETVAL4_FREQ_SEL_SDR104_SHIFT 0
+#define SD4_EMMC_TOP_PRESETVAL4_FREQ_SEL_SDR104_MASK 0x000003FF
+
+#define SD4_EMMC_TOP_BOOTTIMEOUT_OFFSET 0x00000070
+#define SD4_EMMC_TOP_BOOTTIMEOUT_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_BOOTTIMEOUT_TYPE uint32_t
+#define SD4_EMMC_TOP_BOOTTIMEOUT_RESERVED_MASK 0x00000000
+#define SD4_EMMC_TOP_BOOTTIMEOUT_BOOTDATATIMEOUTCTRVALUE_SHIFT 0
+#define SD4_EMMC_TOP_BOOTTIMEOUT_BOOTDATATIMEOUTCTRVALUE_MASK 0xFFFFFFFF
+
+#define SD4_EMMC_TOP_DBGSEL_OFFSET 0x00000074
+#define SD4_EMMC_TOP_DBGSEL_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_DBGSEL_TYPE uint32_t
+#define SD4_EMMC_TOP_DBGSEL_RESERVED_MASK 0xFFFFFFFE
+#define SD4_EMMC_TOP_DBGSEL_DBGSEL_SHIFT 0
+#define SD4_EMMC_TOP_DBGSEL_DBGSEL_MASK 0x00000001
+
+#define SD4_EMMC_TOP_UHS2_PRESETVAL_OFFSET 0x00000074
+#define SD4_EMMC_TOP_UHS2_PRESETVAL_DEFAULT 0x00000000
+#define SD4_EMMC_TOP_UHS2_PRESETVAL_TYPE uint32_t
+#define SD4_EMMC_TOP_UHS2_PRESETVAL_RESERVED_MASK 0xFFFF3800
+#define SD4_EMMC_TOP_UHS2_PRESETVAL_DRVSTRVAL_SHIFT 14
+#define SD4_EMMC_TOP_UHS2_PRESETVAL_DRVSTRVAL_MASK 0x0000C000
+#define SD4_EMMC_TOP_UHS2_PRESETVAL_CLKGENSELVAL_SHIFT 10
+#define SD4_EMMC_TOP_UHS2_PRESETVAL_CLKGENSELVAL_MASK 0x00000400
+#define SD4_EMMC_TOP_UHS2_PRESETVAL_SDCLKFREQSELVAL_SHIFT 0
+#define SD4_EMMC_TOP_UHS2_PRESETVAL_SDCLKFREQSELVAL_MASK 0x000003FF
+
+#define SD4_EMMC_TOP_HCVERSIRQ_OFFSET 0x000000FC
+#define SD4_EMMC_TOP_HCVERSIRQ_DEFAULT 0x10020000
+#define SD4_EMMC_TOP_HCVERSIRQ_TYPE uint32_t
+#define SD4_EMMC_TOP_HCVERSIRQ_RESERVED_MASK 0x0000FF00
+#define SD4_EMMC_TOP_HCVERSIRQ_VENDVER_SHIFT 24
+#define SD4_EMMC_TOP_HCVERSIRQ_VENDVER_MASK 0xFF000000
+#define SD4_EMMC_TOP_HCVERSIRQ_SPECVER_SHIFT 16
+#define SD4_EMMC_TOP_HCVERSIRQ_SPECVER_MASK 0x00FF0000
+#define SD4_EMMC_TOP_HCVERSIRQ_SIRQ_SHIFT 0
+#define SD4_EMMC_TOP_HCVERSIRQ_SIRQ_MASK 0x000000FF
+
+#define SD4_EMMC_TOP_HCVERSIRQ_SD4_OFFSET 0x000000FC
+#define SD4_EMMC_TOP_HCVERSIRQ_SD4_DEFAULT 0x01030000
+#define SD4_EMMC_TOP_HCVERSIRQ_SD4_TYPE uint32_t
+#define SD4_EMMC_TOP_HCVERSIRQ_SD4_RESERVED_MASK 0x0000FF00
+#define SD4_EMMC_TOP_HCVERSIRQ_SD4_VENDVER_SHIFT 24
+#define SD4_EMMC_TOP_HCVERSIRQ_SD4_VENDVER_MASK 0xFF000000
+#define SD4_EMMC_TOP_HCVERSIRQ_SD4_SPECVER_SHIFT 16
+#define SD4_EMMC_TOP_HCVERSIRQ_SD4_SPECVER_MASK 0x00FF0000
+#define SD4_EMMC_TOP_HCVERSIRQ_SD4_SIRQ_SHIFT 0
+#define SD4_EMMC_TOP_HCVERSIRQ_SD4_SIRQ_MASK 0x000000FF
+
+#endif /* BRCM_RDB_SD4_EMMC_TOP_H */
diff --git a/include/drivers/brcm/emmc/emmc_chal_sd.h b/include/drivers/brcm/emmc/emmc_chal_sd.h
new file mode 100644
index 0000000000..8d223f9dde
--- /dev/null
+++ b/include/drivers/brcm/emmc/emmc_chal_sd.h
@@ -0,0 +1,202 @@
+/*
+ * Copyright (c) 2016 - 2020, Broadcom
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CHAL_SD_H
+#define CHAL_SD_H
+
+#include <stddef.h>
+
+#define BASE_CLK_FREQ (200 * 1000 * 1000)
+#define INIT_CLK_FREQ (400 * 1000)
+
+#define SD_ERROR_RECOVERABLE 0
+#define SD_ERROR_NON_RECOVERABLE 1
+
+#define SD_OK 0
+#define SD_FAIL (-1)
+#define SD_INVALID_HANDLE (-2)
+#define SD_CEATA_INIT_ERROR (-3)
+#define SD_RESET_ERROR (-4)
+#define SD_CARD_INIT_ERROR (-5)
+#define SD_INV_DATA_WIDTH (-6)
+#define SD_SET_BUS_WIDTH_ERROR (-7)
+#define SD_DMA_NOT_SUPPORT (-8)
+#define SD_SDIO_READ_ERROR (-9)
+#define SD_SDIO_WRITE_ERROR (-10)
+#define SD_WRITE_ERROR (-11)
+#define SD_READ_ERROR (-12)
+#define SD_READ_SIZE_ERROR (-13)
+#define SD_RW_ADDRESS_ERROR (-14)
+#define SD_XFER_ADDRESS_ERROR (-15)
+#define SD_DATA_XFER_ADDR_ERROR (-16)
+#define SD_DATA_XFER_ERROR (-17)
+#define SD_WRITE_SIZE_ERROR (-18)
+#define SD_CMD_STATUS_UPDATE_ERR (-19)
+#define SD_CMD12_ERROR (-20)
+#define SD_CMD_DATA_ERROR (-21)
+#define SD_CMD_TIMEOUT (-22)
+#define SD_CMD_NO_RESPONSE (-22)
+#define SD_CMD_ABORT_ERROR (-23)
+#define SD_CMD_INVALID (-24)
+#define SD_CMD_RESUME_ERROR (-25)
+#define SD_CMD_ERR_INVALID_RESPONSE (-26)
+#define SD_WAIT_TIMEOUT (-27)
+#define SD_READ_TIMEOUT (-28)
+#define SD_CEATA_REST_ERROR (-29)
+#define SD_INIT_CAED_FAILED (-30)
+#define SD_ERROR_CLOCK_OFFLIMIT (-31)
+#define SD_INV_SLOT (-32)
+
+#define SD_NOR_INTERRUPTS 0x000000FF
+#define SD_ERR_INTERRUPTS 0x03FF0000
+#define SD_CMD_ERROR_INT 0x010F0000
+#define SD_DAT_ERROR_INT 0x02F00000
+#define SD_DAT_TIMEOUT 0x00100000
+
+/* Operation modes */
+#define SD_PIO_MODE 0
+#define SD_INT_MODE 1
+
+/* Support both ADMA and SDMA (for version 2.0 and above) */
+#define SD_DMA_OFF 0
+#define SD_DMA_SDMA 1
+#define SD_DMA_ADMA 2
+
+#define SD_NORMAL_SPEED 0
+#define SD_HIGH_SPEED 1
+
+#define SD_XFER_CARD_TO_HOST 3
+#define SD_XFER_HOST_TO_CARD 4
+
+#define SD_CARD_DETECT_AUTO 0
+#define SD_CARD_DETECT_SD 1
+#define SD_CARD_DETECT_SDIO 2
+#define SD_CARD_DETECT_MMC 3
+#define SD_CARD_DETECT_CEATA 4
+
+#define SD_ABORT_SYNC_MODE 0
+#define SD_ABORT_ASYNC_MODE 1
+
+#define SD_CMD_ERROR_FLAGS (0x18F << 16)
+#define SD_DATA_ERROR_FLAGS (0x70 << 16)
+#define SD_AUTO_CMD12_ERROR_FLAGS (0x9F)
+
+#define SD_CARD_STATUS_ERROR 0x10000000
+#define SD_CMD_MISSING 0x80000000
+#define SD_ERROR_INT 0x8000
+
+#define SD_TRAN_HIGH_SPEED 0x32
+#define SD_CARD_HIGH_CAPACITY 0x40000000
+#define SD_CARD_POWER_UP_STATUS 0x80000000
+
+#define SD_HOST_CORE_TIMEOUT 0x0E
+
+/* SD CARD and Host Controllers bus width */
+#define SD_BUS_DATA_WIDTH_1BIT 0x00
+#define SD_BUS_DATA_WIDTH_4BIT 0x02
+#define SD_BUS_DATA_WIDTH_8BIT 0x20
+
+/* dma boundary settings */
+#define SD_DMA_BOUNDARY_4K 0
+#define SD_DMA_BOUNDARY_8K (1 << 12)
+#define SD_DMA_BOUNDARY_16K (2 << 12)
+#define SD_DMA_BOUNDARY_32K (3 << 12)
+#define SD_DMA_BOUNDARY_64K (4 << 12)
+#define SD_DMA_BOUNDARY_128K (5 << 12)
+#define SD_DMA_BOUNDARY_256K (6 << 12)
+#define SD_DMA_BOUNDARY_512K (7 << 12)
+
+#define SD_CMDR_CMD_NORMAL 0x00000000
+#define SD_CMDR_CMD_SUSPEND 0x00400000
+#define SD_CMDR_CMD_RESUME 0x00800000
+#define SD_CMDR_CMD_ABORT 0x00c00000
+
+#define SD_CMDR_RSP_TYPE_NONE 0x0
+#define SD_CMDR_RSP_TYPE_R2 0x1
+#define SD_CMDR_RSP_TYPE_R3_4 0x2
+#define SD_CMDR_RSP_TYPE_R1_5_6 0x2
+#define SD_CMDR_RSP_TYPE_R1b_5b 0x3
+#define SD_CMDR_RSP_TYPE_S 16
+
+struct sd_ctrl_info {
+ uint32_t blkReg; /* current block register cache value */
+ uint32_t cmdReg; /* current command register cache value */
+ uint32_t argReg; /* current argument register cache value */
+ uint32_t cmdIndex; /* current command index */
+ uint32_t cmdStatus; /* current command status, cmd/data compelete */
+ uint16_t rca; /* relative card address */
+ uint32_t ocr; /* operation codition */
+ uint32_t eventList; /* events list */
+ uint32_t blkGapEnable;
+
+ uint32_t capability; /* controller's capbilities */
+ uint32_t maxCurrent; /* maximum current supported */
+ uint32_t present; /* if card is inserted or removed */
+ uint32_t version; /* SD spec version 1.0 or 2.0 */
+ uint32_t vendor; /* vendor number */
+
+ uintptr_t sdRegBaseAddr; /* sdio control registers */
+ uintptr_t hostRegBaseAddr; /* SD Host control registers */
+};
+
+struct sd_cfg {
+ uint32_t mode; /* interrupt or polling */
+ uint32_t dma; /* dma enabled or disabled */
+ uint32_t retryLimit; /* command retry limit */
+ uint32_t speedMode; /* speed mode, 0 standard, 1 high speed */
+ uint32_t voltage; /* voltage level */
+ uint32_t blockSize; /* access block size (512 for HC card) */
+ uint32_t dmaBoundary; /* dma address boundary */
+ uint32_t detSignal; /* card det signal src, for test purpose only */
+ uint32_t rdWaiting;
+ uint32_t wakeupOut;
+ uint32_t wakeupIn;
+ uint32_t wakeupInt;
+ uint32_t wfe_retry;
+ uint32_t gapInt;
+ uint32_t readWait;
+ uint32_t led;
+};
+
+struct sd_dev {
+ struct sd_cfg cfg; /* SD configuration */
+ struct sd_ctrl_info ctrl; /* SD info */
+};
+
+int32_t chal_sd_start(CHAL_HANDLE *sdHandle, uint32_t mode,
+ uint32_t sdBase, uint32_t hostBase);
+int32_t chal_sd_config(CHAL_HANDLE *sdHandle, uint32_t speed,
+ uint32_t retry, uint32_t boundary,
+ uint32_t blkSize, uint32_t dma);
+int32_t chal_sd_stop(void);
+int32_t chal_sd_set_dma(CHAL_HANDLE *sdHandle, uint32_t mode);
+uintptr_t chal_sd_get_dma_addr(CHAL_HANDLE *handle);
+int32_t chal_sd_config_bus_width(CHAL_HANDLE *sdHandle, int32_t width);
+int32_t chal_sd_send_cmd(CHAL_HANDLE *sdHandle, uint32_t cmdIndex,
+ uint32_t arg, uint32_t options);
+int32_t chal_sd_set_dma_addr(CHAL_HANDLE *sdHandle, uintptr_t address);
+int32_t chal_sd_set_clock(CHAL_HANDLE *sdHandle,
+ uint32_t div_ctrl_setting, uint32_t on);
+uint32_t chal_sd_freq_2_div_ctrl_setting(uint32_t desired_freq);
+int32_t chal_sd_setup_xfer(CHAL_HANDLE *sdHandle, uint8_t *data,
+ uint32_t length, int32_t dir);
+int32_t chal_sd_write_buffer(CHAL_HANDLE *sdHandle, uint32_t length,
+ uint8_t *data);
+int32_t chal_sd_read_buffer(CHAL_HANDLE *sdHandle, uint32_t length,
+ uint8_t *data);
+int32_t chal_sd_reset_line(CHAL_HANDLE *sdHandle, uint32_t line);
+int32_t chal_sd_get_response(CHAL_HANDLE *sdHandle, uint32_t *resp);
+int32_t chal_sd_clear_pending_irq(CHAL_HANDLE *sdHandle);
+int32_t chal_sd_get_irq_status(CHAL_HANDLE *sdHandle);
+int32_t chal_sd_clear_irq(CHAL_HANDLE *sdHandle, uint32_t mask);
+uint32_t chal_sd_get_present_status(CHAL_HANDLE *sdHandle);
+int32_t chal_sd_get_atuo12_error(CHAL_HANDLE *sdHandle);
+void chal_sd_set_speed(CHAL_HANDLE *sdHandle, uint32_t speed);
+int32_t chal_sd_check_cap(CHAL_HANDLE *sdHandle, uint32_t cap);
+void chal_sd_set_irq_signal(CHAL_HANDLE *sdHandle, uint32_t mask,
+ uint32_t state);
+void chal_sd_dump_fifo(CHAL_HANDLE *sdHandle);
+#endif /* CHAL_SD_H */
diff --git a/include/drivers/brcm/emmc/emmc_chal_types.h b/include/drivers/brcm/emmc/emmc_chal_types.h
new file mode 100644
index 0000000000..9563273adb
--- /dev/null
+++ b/include/drivers/brcm/emmc/emmc_chal_types.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2016 - 2020, Broadcom
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#ifndef CHAL_TYPES_H
+#define CHAL_TYPES_H
+
+#include <stdint.h>
+
+//
+// Generic cHAL handler
+//
+#ifndef CHAL_HANDLE
+ typedef void *CHAL_HANDLE; ///< void pointer (32 bits wide)
+#endif
+
+#endif /* _CHAL_TYPES_H_ */
diff --git a/include/drivers/brcm/emmc/emmc_csl_sd.h b/include/drivers/brcm/emmc/emmc_csl_sd.h
new file mode 100644
index 0000000000..52b8bc84bd
--- /dev/null
+++ b/include/drivers/brcm/emmc/emmc_csl_sd.h
@@ -0,0 +1,96 @@
+/*
+ * Copyright (c) 2016 - 2020, Broadcom
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CSL_SD_H
+#define CSL_SD_H
+
+#define SD_CLOCK_BASE 104000000
+#define SD_CLOCK_52MHZ 52000000
+#define SD_CLOCK_26MHZ 26000000
+#define SD_CLOCK_17MHZ 17330000
+#define SD_CLOCK_13MHZ 13000000
+#define SD_CLOCK_10MHZ 10000000
+#define SD_CLOCK_9MHZ 9000000
+#define SD_CLOCK_7MHZ 7000000
+#define SD_CLOCK_5MHZ 5000000
+#define SD_CLOCK_1MHZ 1000000
+#define SD_CLOCK_400KHZ 400000
+
+#define SD_DRIVE_STRENGTH_MASK 0x38000000
+#if defined(_BCM213x1_) || defined(_BCM21551_) || defined(_ATHENA_)
+#define SD_DRIVE_STRENGTH 0x28000000
+#elif defined(_BCM2153_)
+#define SD_DRIVE_STRENGTH 0x38000000
+#else
+#define SD_DRIVE_STRENGTH 0x00000000
+#endif
+
+#define SD_NUM_HOST 2
+
+#define SD_CARD_UNLOCK 0
+#define SD_CARD_LOCK 0x4
+#define SD_CARD_CLEAR_PWD 0x2
+#define SD_CARD_SET_PWD 0x1
+#define SD_CARD_ERASE_PWD 0x8
+
+#define SD_CARD_LOCK_STATUS 0x02000000
+#define SD_CARD_UNLOCK_STATUS 0x01000000
+
+#define SD_CMD_ERROR_FLAGS (0x18F << 16)
+#define SD_DATA_ERROR_FLAGS (0x70 << 16)
+#define SD_AUTO_CMD12_ERROR_FLAGS (0x9F)
+#define SD_CARD_STATUS_ERROR 0x10000000
+#define SD_CMD_MISSING 0x80000000
+
+#define SD_TRAN_HIGH_SPEED 0x32
+#define SD_CARD_HIGH_CAPACITY 0x40000000
+#define SD_CARD_POWER_UP_STATUS 0x80000000
+
+struct sd_dev_info {
+ uint32_t mode; /* interrupt or polling */
+ uint32_t dma; /* dma enabled or disabled */
+ uint32_t voltage; /* voltage level */
+ uint32_t slot; /* if the HC is locatd at slot 0 or slot 1 */
+ uint32_t version; /* 1.0 or 2.0 */
+ uint32_t curSystemAddr; /* system address */
+ uint32_t dataWidth; /* data width for the controller */
+ uint32_t clock; /* clock rate */
+ uint32_t status; /* if device is active on transfer or not */
+};
+
+void data_xfer_setup(struct sd_handle *handle, uint8_t *data,
+ uint32_t length, int dir);
+int reset_card(struct sd_handle *handle);
+int reset_host_ctrl(struct sd_handle *handle);
+int init_card(struct sd_handle *handle, int detection);
+int init_mmc_card(struct sd_handle *handle);
+int write_buffer(struct sd_handle *handle, uint32_t len, uint8_t *buffer);
+int read_buffer(struct sd_handle *handle, uint32_t len, uint8_t *buffer);
+int select_blk_sz(struct sd_handle *handle, uint16_t size);
+int check_error(struct sd_handle *handle, uint32_t ints);
+
+int process_data_xfer(struct sd_handle *handle, uint8_t *buffer,
+ uint32_t addr, uint32_t length, int dir);
+int read_block(struct sd_handle *handle, uint8_t *dst, uint32_t addr,
+ uint32_t len);
+#ifdef INCLUDE_EMMC_DRIVER_ERASE_CODE
+int erase_card(struct sd_handle *handle, uint32_t addr, uint32_t blocks);
+#endif
+int write_block(struct sd_handle *handle, uint8_t *src, uint32_t addr,
+ uint32_t len);
+int process_cmd_response(struct sd_handle *handle, uint32_t cmdIndex,
+ uint32_t rsp0, uint32_t rsp1, uint32_t rsp2,
+ uint32_t rsp3, struct sd_resp *resp);
+int32_t set_config(struct sd_handle *handle, uint32_t speed,
+ uint32_t retry, uint32_t dma, uint32_t dmaBound,
+ uint32_t blkSize, uint32_t wfe_retry);
+
+uint32_t wait_for_event(struct sd_handle *handle, uint32_t mask,
+ uint32_t retry);
+int set_boot_config(struct sd_handle *handle, uint32_t config);
+
+int mmc_cmd1(struct sd_handle *handle);
+#endif /* CSL_SD_H */
diff --git a/include/drivers/brcm/emmc/emmc_csl_sdcmd.h b/include/drivers/brcm/emmc/emmc_csl_sdcmd.h
new file mode 100644
index 0000000000..425603f898
--- /dev/null
+++ b/include/drivers/brcm/emmc/emmc_csl_sdcmd.h
@@ -0,0 +1,168 @@
+/*
+ * Copyright (c) 2016 - 2020, Broadcom
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CSL_SD_CMD_H
+#define CSL_SD_CMD_H
+
+#define SD_CMD_OK 0
+#define SD_CMD_ERROR -1
+
+#define SD_CMD_ERR_NO_IO_FUNC 5
+#define SD_CMD_ERR_INVALID_PARAMETER 6
+#define SD_CMD_ERR_R1_ILLEGAL_COMMAND 7
+#define SD_CMD_ERR_R1_COM_CRC_ERROR 8
+#define SD_CMD_ERR_R1_FUNC_NUM_ERROR 9
+#define SD_CMD_ERR_R1_ADDRESS_ERROR 10
+#define SD_CMD_ERR_R1_PARAMETER_ERROR 11
+#define SD_CMD_ERR_DATA_ERROR_TOKEN 12
+#define SD_CMD_ERR_DATA_NOT_ACCEPTED 13
+#define SD_CMD7_ARG_RCA_SHIFT 16
+
+#define SD_CARD_STATUS_PENDING 0x01
+#define SD_CARD_STATUS_BUFFER_OVERFLOW 0x01
+#define SD_CARD_STATUS_DEVICE_BUSY 0x02
+#define SD_CARD_STATUS_UNSUCCESSFUL 0x03
+#define SD_CARD_STATUS_NOT_IMPLEMENTED 0x04
+#define SD_CARD_STATUS_ACCESS_VIOLATION 0x05
+#define SD_CARD_STATUS_INVALID_HANDLE 0x06
+#define SD_CARD_STATUS_INVALID_PARAMETER 0x07
+#define SD_CARD_STATUS_NO_SUCH_DEVICE 0x08
+#define SD_CARD_STATUS_INVALID_DEVICE_REQUEST 0x09
+#define SD_CARD_STATUS_NO_MEMORY 0x0A
+#define SD_CARD_STATUS_BUS_DRIVER_NOT_READY 0x0B
+#define SD_CARD_STATUS_DATA_ERROR 0x0C
+#define SD_CARD_STATUS_CRC_ERROR 0x0D
+#define SD_CARD_STATUS_INSUFFICIENT_RESOURCES 0x0E
+#define SD_CARD_STATUS_DEVICE_NOT_CONNECTED 0x10
+#define SD_CARD_STATUS_DEVICE_REMOVED 0x11
+#define SD_CARD_STATUS_DEVICE_NOT_RESPONDING 0x12
+#define SD_CARD_STATUS_CANCELED 0x13
+#define SD_CARD_STATUS_RESPONSE_TIMEOUT 0x14
+#define SD_CARD_STATUS_DATA_TIMEOUT 0x15
+#define SD_CARD_STATUS_DEVICE_RESPONSE_ERROR 0x16
+#define SD_CARD_STATUS_DEVICE_UNSUPPORTED 0x17
+
+/* Response structure */
+struct sd_r2_resp {
+ uint32_t rsp4; /* 127:96 */
+ uint32_t rsp3; /* 95:64 */
+ uint32_t rsp2; /* 63:32 */
+ uint32_t rsp1; /* 31:0 */
+};
+
+struct sd_r3_resp {
+ uint32_t ocr;
+};
+
+struct sd_r4_resp {
+ uint8_t cardReady;
+ uint8_t funcs;
+ uint8_t memPresent;
+ uint32_t ocr;
+};
+
+struct sd_r5_resp {
+ uint8_t data;
+};
+
+struct sd_r6_resp {
+ uint16_t rca;
+ uint16_t cardStatus;
+};
+
+struct sd_r7_resp {
+ uint16_t rca;
+};
+
+struct sd_resp {
+ uint8_t r1;
+ uint32_t cardStatus;
+ uint32_t rawData[4];
+ union {
+ struct sd_r2_resp r2;
+ struct sd_r3_resp r3;
+ struct sd_r4_resp r4;
+ struct sd_r5_resp r5;
+ struct sd_r6_resp r6;
+ struct sd_r7_resp r7;
+ } data;
+};
+
+struct sd_card_info {
+ uint32_t type; /* card type SD, MMC or SDIO */
+ uint64_t size; /* card size */
+ uint32_t speed; /* card speed */
+ uint32_t voltage; /* voltage supported */
+ uint32_t mId; /* manufacturer ID */
+ uint32_t oId; /* OEM ID */
+ uint32_t classes; /* card class */
+ uint32_t name1; /* product name part 1 */
+ uint32_t name2; /* product name part 2 */
+ uint32_t revision; /* revison */
+ uint32_t sn; /* serial number */
+ uint32_t numIoFuns; /* total I/O function number */
+ uint32_t maxRdBlkLen; /* max read block length */
+ uint32_t maxWtBlkLen; /* max write block length */
+ uint32_t blkMode; /* sdio card block mode support */
+ uint32_t f0Cis; /* sdio card block mode support */
+ uint32_t f1Cis; /* sdio card block mode support */
+
+ uint8_t partRead; /* partial block read allowed */
+ uint8_t partWrite; /* partial block write allowed */
+ uint8_t dsr; /* card DSR */
+ uint8_t rdCurMin; /* min current for read */
+ uint8_t rdCurMax; /* max current for read */
+ uint8_t wtCurMin; /* min current for write */
+ uint8_t wtCurMax; /* max current for write */
+ uint8_t erase; /* erase enable */
+ uint8_t eraseSecSize; /* erase sector size */
+ uint8_t proGrpSize; /* write protection group size */
+ uint8_t protect; /* permanent write protection or not */
+ uint8_t tmpProt; /* temp write protection or not */
+ uint8_t wtSpeed; /* write speed relatively to read */
+ uint8_t version; /* card version 0:1.0 - 1.01, 1:1.10, 2:2.0 */
+ uint8_t eraseState; /* if the data will be 0 or 1 after erase */
+ uint8_t bus; /* data with supported */
+ uint8_t security; /* security support 0, 2:1.01 3:2.0 */
+ uint8_t format; /* file format */
+ uint8_t fileGrp; /* file group */
+ char pwd[20]; /* password */
+};
+
+struct sd_handle {
+ struct sd_dev *device;
+ struct sd_card_info *card;
+};
+
+int sd_cmd0(struct sd_handle *handle);
+int sd_cmd1(struct sd_handle *handle, uint32_t initOcr, uint32_t *ocr);
+int sd_cmd2(struct sd_handle *handle);
+int sd_cmd3(struct sd_handle *handle);
+int sd_cmd7(struct sd_handle *handle, uint32_t rca);
+int sd_cmd9(struct sd_handle *handle, struct sd_card_data *card);
+int sd_cmd13(struct sd_handle *handle, uint32_t *status);
+int sd_cmd16(struct sd_handle *handle, uint32_t blockLen);
+int sd_cmd17(struct sd_handle *handle,
+ uint32_t addr, uint32_t len, uint8_t *buffer);
+int sd_cmd18(struct sd_handle *handle,
+ uint32_t addr, uint32_t len, uint8_t *buffer);
+#ifdef INCLUDE_EMMC_DRIVER_WRITE_CODE
+int sd_cmd24(struct sd_handle *handle,
+ uint32_t addr, uint32_t len, uint8_t *buffer);
+int sd_cmd25(struct sd_handle *handle,
+ uint32_t addr, uint32_t len, uint8_t *buffer);
+#endif
+#ifdef INCLUDE_EMMC_DRIVER_ERASE_CODE
+int sd_cmd35(struct sd_handle *handle, uint32_t start);
+int sd_cmd36(struct sd_handle *handle, uint32_t end);
+int sd_cmd38(struct sd_handle *handle);
+#endif
+int mmc_cmd6(struct sd_handle *handle, uint32_t argument);
+int mmc_cmd8(struct sd_handle *handle, uint8_t *extCsdReg);
+
+int send_cmd(struct sd_handle *handle, uint32_t cmdIndex,
+ uint32_t argument, uint32_t options, struct sd_resp *resp);
+#endif /* CSL_SD_CMD_H */
diff --git a/include/drivers/brcm/emmc/emmc_csl_sdprot.h b/include/drivers/brcm/emmc/emmc_csl_sdprot.h
new file mode 100644
index 0000000000..597e1e0876
--- /dev/null
+++ b/include/drivers/brcm/emmc/emmc_csl_sdprot.h
@@ -0,0 +1,435 @@
+/*
+ * Copyright (c) 2016 - 2020, Broadcom
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CSL_SD_PROT_H
+#define CSL_SD_PROT_H
+
+#define SD_CARD_UNKNOWN 0 /* bad type or unrecognized */
+#define SD_CARD_SD 1 /* IO only card */
+#define SD_CARD_SDIO 2 /* memory only card */
+#define SD_CARD_COMBO 3 /* IO and memory combo card */
+#define SD_CARD_MMC 4 /* memory only card */
+#define SD_CARD_CEATA 5 /* IO and memory combo card */
+
+#define SD_IO_FIXED_ADDRESS 0 /* fix Address */
+#define SD_IO_INCREMENT_ADDRESS 1
+
+#define SD_HIGH_CAPACITY_CARD 0x40000000
+
+#define MMC_CMD_IDLE_RESET_ARG 0xF0F0F0F0
+
+/* Supported operating voltages are 3.2-3.3 and 3.3-3.4 */
+#define MMC_OCR_OP_VOLT 0x00300000
+/* Enable sector access mode */
+#define MMC_OCR_SECTOR_ACCESS_MODE 0x40000000
+
+/* command index */
+#define SD_CMD_GO_IDLE_STATE 0 /* mandatory for SDIO */
+#define SD_CMD_SEND_OPCOND 1
+#define SD_CMD_ALL_SEND_CID 2
+#define SD_CMD_MMC_SET_RCA 3
+#define SD_CMD_MMC_SET_DSR 4
+#define SD_CMD_IO_SEND_OP_COND 5 /* mandatory for SDIO */
+#define SD_ACMD_SET_BUS_WIDTH 6
+#define SD_CMD_SWITCH_FUNC 6
+#define SD_CMD_SELECT_DESELECT_CARD 7
+#define SD_CMD_READ_EXT_CSD 8
+#define SD_CMD_SEND_CSD 9
+#define SD_CMD_SEND_CID 10
+#define SD_CMD_STOP_TRANSMISSION 12
+#define SD_CMD_SEND_STATUS 13
+#define SD_ACMD_SD_STATUS 13
+#define SD_CMD_GO_INACTIVE_STATE 15
+#define SD_CMD_SET_BLOCKLEN 16
+#define SD_CMD_READ_SINGLE_BLOCK 17
+#define SD_CMD_READ_MULTIPLE_BLOCK 18
+#define SD_CMD_WRITE_BLOCK 24
+#define SD_CMD_WRITE_MULTIPLE_BLOCK 25
+#define SD_CMD_PROGRAM_CSD 27
+#define SD_CMD_SET_WRITE_PROT 28
+#define SD_CMD_CLR_WRITE_PROT 29
+#define SD_CMD_SEND_WRITE_PROT 30
+#define SD_CMD_ERASE_WR_BLK_START 32
+#define SD_CMD_ERASE_WR_BLK_END 33
+#define SD_CMD_ERASE_GROUP_START 35
+#define SD_CMD_ERASE_GROUP_END 36
+#define SD_CMD_ERASE 38
+#define SD_CMD_LOCK_UNLOCK 42
+#define SD_CMD_IO_RW_DIRECT 52 /* mandatory for SDIO */
+#define SD_CMD_IO_RW_EXTENDED 53 /* mandatory for SDIO */
+#define SD_CMD_APP_CMD 55
+#define SD_CMD_GEN_CMD 56
+#define SD_CMD_READ_OCR 58
+#define SD_CMD_CRC_ON_OFF 59 /* mandatory for SDIO */
+#define SD_ACMD_SEND_NUM_WR_BLOCKS 22
+#define SD_ACMD_SET_WR_BLOCK_ERASE_CNT 23
+#define SD_ACMD_SD_SEND_OP_COND 41
+#define SD_ACMD_SET_CLR_CARD_DETECT 42
+#define SD_ACMD_SEND_SCR 51
+
+/* response parameters */
+#define SD_RSP_NO_NONE 0
+#define SD_RSP_NO_1 1
+#define SD_RSP_NO_2 2
+#define SD_RSP_NO_3 3
+#define SD_RSP_NO_4 4
+#define SD_RSP_NO_5 5
+#define SD_RSP_NO_6 6
+
+/* Modified R6 response (to CMD3) */
+#define SD_RSP_MR6_COM_CRC_ERROR 0x8000
+#define SD_RSP_MR6_ILLEGAL_COMMAND 0x4000
+#define SD_RSP_MR6_ERROR 0x2000
+
+/* Modified R1 in R4 Response (to CMD5) */
+#define SD_RSP_MR1_SBIT 0x80
+#define SD_RSP_MR1_PARAMETER_ERROR 0x40
+#define SD_RSP_MR1_RFU5 0x20
+#define SD_RSP_MR1_FUNC_NUM_ERROR 0x10
+#define SD_RSP_MR1_COM_CRC_ERROR 0x80
+#define SD_RSP_MR1_ILLEGAL_COMMAND 0x40
+#define SD_RSP_MR1_RFU1 0x20
+#define SD_RSP_MR1_IDLE_STATE 0x01
+
+/* R5 response (to CMD52 and CMD53) */
+#define SD_RSP_R5_COM_CRC_ERROR 0x80
+#define SD_RSP_R5_ILLEGAL_COMMAND 0x40
+#define SD_RSP_R5_IO_CURRENTSTATE1 0x20
+#define SD_RSP_R5_IO_CURRENTSTATE0 0x10
+#define SD_RSP_R5_ERROR 0x80
+#define SD_RSP_R5_RFU 0x40
+#define SD_RSP_R5_FUNC_NUM_ERROR 0x20
+#define SD_RSP_R5_OUT_OF_RANGE 0x01
+
+/* argument for SD_CMD_IO_RW_DIRECT and SD_CMD_IO_RW_EXTENDED */
+#define SD_OP_READ 0 /* Read_Write */
+#define SD_OP_WRITE 1 /* Read_Write */
+
+#define SD_RW_NORMAL 0 /* no RAW */
+#define SD_RW_RAW 1 /* RAW */
+
+#define SD_BYTE_MODE 0 /* Byte Mode */
+#define SD_BLOCK_MODE 1 /* BlockMode */
+
+#define SD_FIXED_ADDRESS 0 /* fix Address */
+#define SD_INCREMENT_ADDRESS 1 /* IncrementAddress */
+
+#define SD_CMD5_ARG_IO_OCR_MASK 0x00FFFFFF
+#define SD_CMD5_ARG_IO_OCR_SHIFT 0
+#define SD_CMD55_ARG_RCA_SHIFT 16
+#define SD_CMD59_ARG_CRC_OPTION_MASK 0x01
+#define SD_CMD59_ARG_CRC_OPTION_SHIFT 0
+
+/* SD_CMD_IO_RW_DIRECT Argument */
+#define SdioIoRWDirectArg(rw, raw, func, addr, data) \
+ (((rw & 1) << 31) | ((func & 0x7) << 28) | \
+ ((raw & 1) << 27) | ((addr & 0x1FFFF) << 9) | \
+ (data & 0xFF))
+
+/* build SD_CMD_IO_RW_EXTENDED Argument */
+#define SdioIoRWExtArg(rw, blk, func, addr, inc_addr, count) \
+ (((rw & 1) << 31) | ((func & 0x7) << 28) | \
+ ((blk & 1) << 27) | ((inc_addr & 1) << 26) | \
+ ((addr & 0x1FFFF) << 9) | (count & 0x1FF))
+
+/*
+ * The Common I/O area shall be implemented on all SDIO cards and
+ * is accessed the the host via I/O reads and writes to function 0,
+ * the registers within the CIA are provided to enable/disable
+ * the operationo fthe i/o funciton.
+ */
+
+/* cccr_sdio_rev */
+#define SDIO_REV_SDIOID_MASK 0xf0 /* SDIO spec revision number */
+#define SDIO_REV_CCCRID_MASK 0x0f /* CCCR format version number */
+
+/* sd_rev */
+#define SDIO_REV_PHY_MASK 0x0f /* SD format version number */
+#define SDIO_FUNC_ENABLE_1 0x02 /* function 1 I/O enable */
+#define SDIO_FUNC_READY_1 0x02 /* function 1 I/O ready */
+#define SDIO_INTR_CTL_FUNC1_EN 0x2 /* interrupt enable for function 1 */
+#define SDIO_INTR_CTL_MASTER_EN 0x1 /* interrupt enable master */
+#define SDIO_INTR_STATUS_FUNC1 0x2 /* interrupt pending for function 1 */
+#define SDIO_IO_ABORT_RESET_ALL 0x08 /* I/O card reset */
+#define SDIO_IO_ABORT_FUNC_MASK 0x07 /* abort selection: function x */
+#define SDIO_BUS_CARD_DETECT_DIS 0x80 /* Card Detect disable */
+#define SDIO_BUS_SPI_CONT_INTR_CAP 0x40 /* support continuous SPI interrupt */
+#define SDIO_BUS_SPI_CONT_INTR_EN 0x20 /* continuous SPI interrupt enable */
+#define SDIO_BUS_DATA_WIDTH_MASK 0x03 /* bus width mask */
+#define SDIO_BUS_DATA_WIDTH_4BIT 0x02 /* bus width 4-bit mode */
+#define SDIO_BUS_DATA_WIDTH_1BIT 0x00 /* bus width 1-bit mode */
+
+/* capability */
+#define SDIO_CAP_4BLS 0x80 /* 4-bit support for low speed card */
+#define SDIO_CAP_LSC 0x40 /* low speed card */
+#define SDIO_CAP_E4MI 0x20 /* enable int between block in 4-bit mode */
+#define SDIO_CAP_S4MI 0x10 /* support int between block in 4-bit mode */
+#define SDIO_CAP_SBS 0x08 /* support suspend/resume */
+#define SDIO_CAP_SRW 0x04 /* support read wait */
+#define SDIO_CAP_SMB 0x02 /* support multi-block transfer */
+#define SDIO_CAP_SDC 0x01 /* Support Direct cmd during multi-uint8 transfer */
+
+/* CIA FBR1 registers */
+#define SDIO_FUNC1_INFO 0x100 /* basic info for function 1 */
+#define SDIO_FUNC1_EXT 0x101 /* extension of standard I/O device */
+#define SDIO_CIS_FUNC1_BASE_LOW 0x109 /* function 1 cis address bit 0-7 */
+#define SDIO_CIS_FUNC1_BASE_MID 0x10A /* function 1 cis address bit 8-15 */
+#define SDIO_CIS_FUNC1_BASE_HIGH 0x10B /* function 1 cis address bit 16 */
+#define SDIO_CSA_BASE_LOW 0x10C /* CSA base address uint8_t 0 */
+#define SDIO_CSA_BASE_MID 0x10D /* CSA base address uint8_t 1 */
+#define SDIO_CSA_BASE_HIGH 0x10E /* CSA base address uint8_t 2 */
+#define SDIO_CSA_DATA_OFFSET 0x10F /* CSA data register */
+#define SDIO_IO_BLK_SIZE_LOW 0x110 /* I/O block size uint8_t 0 */
+#define SDIO_IO_BLK_SIZE_HIGH 0x111 /* I/O block size uint8_t 1 */
+
+/* SD_SDIO_FUNC1_INFO bits */
+#define SDIO_FUNC1_INFO_DIC 0x0f /* device interface code */
+#define SDIO_FUNC1_INFO_CSA 0x40 /* CSA support flag */
+#define SDIO_FUNC1_INFO_CSA_EN 0x80 /* CSA enabled */
+
+/* SD_SDIO_FUNC1_EXT bits */
+#define SDIO_FUNC1_EXT_SHP 0x03 /* support high power */
+#define SDIO_FUNC1_EXT_EHP 0x04 /* enable high power */
+
+/* devctr */
+/* I/O device interface code */
+#define SDIO_DEVCTR_DEVINTER 0x0f
+/* support CSA */
+#define SDIO_DEVCTR_CSA_SUP 0x40
+/* enable CSA */
+#define SDIO_DEVCTR_CSA_EN 0x80
+
+/* ext_dev */
+/* supports high-power mask */
+#define SDIO_HIGHPWR_SUPPORT_M 0x3
+/* enable high power */
+#define SDIO_HIGHPWR_EN 0x4
+/* standard power function(up to 200mA */
+#define SDIO_HP_STD 0
+/* need high power to operate */
+#define SDIO_HP_REQUIRED 0x2
+/* can work with standard power, but prefer high power */
+#define SDIO_HP_DESIRED 0x3
+
+/* misc define */
+/* macro to calculate fbr register base */
+#define FBR_REG_BASE(n) (n*0x100)
+#define SDIO_FUNC_0 0
+#define SDIO_FUNC_1 1
+#define SDIO_FUNC_2 2
+#define SDIO_FUNC_3 3
+#define SDIO_FUNC_4 4
+#define SDIO_FUNC_5 5
+#define SDIO_FUNC_6 6
+#define SDIO_FUNC_7 7
+
+/* maximum block size for block mode operation */
+#define SDIO_MAX_BLOCK_SIZE 2048
+/* minimum block size for block mode operation */
+#define SDIO_MIN_BLOCK_SIZE 1
+
+/* Card registers: status bit position */
+#define SDIO_STATUS_OUTOFRANGE 31
+#define SDIO_STATUS_COMCRCERROR 23
+#define SDIO_STATUS_ILLEGALCOMMAND 22
+#define SDIO_STATUS_ERROR 19
+#define SDIO_STATUS_IOCURRENTSTATE3 12
+#define SDIO_STATUS_IOCURRENTSTATE2 11
+#define SDIO_STATUS_IOCURRENTSTATE1 10
+#define SDIO_STATUS_IOCURRENTSTATE0 9
+#define SDIO_STATUS_FUN_NUM_ERROR 4
+
+#define GET_SDIOCARD_STATUS(x) ((x >> 9) & 0x0f)
+#define SDIO_STATUS_STATE_IDLE 0
+#define SDIO_STATUS_STATE_READY 1
+#define SDIO_STATUS_STATE_IDENT 2
+#define SDIO_STATUS_STATE_STBY 3
+#define SDIO_STATUS_STATE_TRAN 4
+#define SDIO_STATUS_STATE_DATA 5
+#define SDIO_STATUS_STATE_RCV 6
+#define SDIO_STATUS_STATE_PRG 7
+#define SDIO_STATUS_STATE_DIS 8
+
+/* sprom */
+#define SBSDIO_SPROM_CS 0x10000 /* command and status */
+#define SBSDIO_SPROM_INFO 0x10001 /* info register */
+#define SBSDIO_SPROM_DATA_LOW 0x10002 /* indirect access data uint8_t 0 */
+#define SBSDIO_SPROM_DATA_HIGH 0x10003 /* indirect access data uint8_t 1 */
+#define SBSDIO_SPROM_ADDR_LOW 0x10004 /* indirect access addr uint8_t 0 */
+#define SBSDIO_SPROM_ADDR_HIGH 0x10005 /* indirect access addr uint8_t 0 */
+#define SBSDIO_CHIP_CTRL_DATA 0x10006 /* xtal_pu data output */
+#define SBSDIO_CHIP_CTRL_EN 0x10007 /* xtal_pu enable */
+#define SBSDIO_WATERMARK 0x10008 /* retired in rev 7 */
+#define SBSDIO_DEVICE_CTL 0x10009 /* control busy signal generation */
+
+#define SBSDIO_SPROM_IDLE 0
+#define SBSDIO_SPROM_WRITE 1
+#define SBSDIO_SPROM_READ 2
+#define SBSDIO_SPROM_WEN 4
+#define SBSDIO_SPROM_WDS 7
+#define SBSDIO_SPROM_DONE 8
+
+/* SBSDIO_SPROM_INFO */
+#define SBSDIO_SROM_SZ_MASK 0x03 /* SROM size, 1: 4k, 2: 16k */
+#define SBSDIO_SROM_BLANK 0x04 /* depreciated in corerev 6 */
+#define SBSDIO_SROM_OTP 0x80 /* OTP present */
+
+/* SBSDIO_CHIP_CTRL */
+/* or'd with onchip xtal_pu, 1: power on oscillator */
+#define SBSDIO_CHIP_CTRL_XTAL 0x01
+
+/* SBSDIO_WATERMARK */
+/* number of bytes minus 1 for sd device to wait before sending data to host */
+#define SBSDIO_WATERMARK_MASK 0x3f
+
+/* SBSDIO_DEVICE_CTL */
+/* 1: device will assert busy signal when receiving CMD53 */
+#define SBSDIO_DEVCTL_SETBUSY 0x01
+/* 1: assertion of sdio interrupt is synchronous to the sdio clock */
+#define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02
+
+/* function 1 OCP space */
+/* sb offset addr is <= 15 bits, 32k */
+#define SBSDIO_SB_OFT_ADDR_MASK 0x07FFF
+#define SBSDIO_SB_OFT_ADDR_LIMIT 0x08000
+/* sdsdio function 1 OCP space has 16/32 bit section */
+#define SBSDIO_SB_ACCESS_2_4B_FLAG 0x08000
+
+/* direct(mapped) cis space */
+/* MAPPED common CIS address */
+#define SBSDIO_CIS_BASE_COMMON 0x1000
+/* function 0(common) cis size in bytes */
+#define SBSDIO_CIS_FUNC0_LIMIT 0x020
+/* funciton 1 cis size in bytes */
+#define SBSDIO_CIS_SIZE_LIMIT 0x200
+/* cis offset addr is < 17 bits */
+#define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF
+/* manfid tuple length, include tuple, link bytes */
+#define SBSDIO_CIS_MANFID_TUPLE_LEN 6
+
+/* indirect cis access (in sprom) */
+/* 8 control bytes first, CIS starts from 8th uint8_t */
+#define SBSDIO_SPROM_CIS_OFFSET 0x8
+/* sdio uint8_t mode: maximum length of one data comamnd */
+#define SBSDIO_BYTEMODE_DATALEN_MAX 64
+/* 4317 supports less */
+#define SBSDIO_BYTEMODE_DATALEN_MAX_4317 52
+/* sdio core function one address mask */
+#define SBSDIO_CORE_ADDR_MASK 0x1FFFF
+
+/* CEATA defines */
+#define CEATA_EXT_CSDBLOCK_SIZE 512
+#define CEATA_FAST_IO 39
+#define CEATA_MULTIPLE_REGISTER_RW 60
+#define CEATA_MULTIPLE_BLOCK_RW 61
+
+/* defines CE ATA task file registers */
+#define CEATA_SCT_CNT_EXP_REG 0x02
+#define CEATA_LBA_LOW_EXP_REG 0x03
+#define CEATA_LBA_MID_EXP_REG 0x04
+#define CEATA_LBA_HIGH_EXP_REG 0x05
+#define CEATA_CNTRL_REG 0x06
+#define CEATA_FEATURE_REG 0x09 /* write */
+#define CEATA_ERROR_REG 0x09 /* read */
+#define CEATA_SCT_CNT_REG 0x0A
+#define CEATA_LBA_LOW_REG 0x0B
+#define CEATA_LBA_MID_REG 0x0C
+#define CEATA_LBA_HIGH_REG 0x0D
+#define CEATA_DEV_HEAD_REG 0x0E
+#define CEATA_STA_REG 0x0F /* read */
+#define CEATA_CMD_REG 0x0F /* write */
+
+/* defines CEATA control and status registers for ce ata client driver */
+#define CEATA_SCR_TEMPC_REG 0x80
+#define CEATA_SCR_TEMPMAXP_REG 0x84
+#define CEATA_TEMPMINP_REG 0x88
+#define CEATA_SCR_STATUS_REG 0x8C
+#define CEATA_SCR_REALLOCSA_REG 0x90
+#define CEATA_SCR_ERETRACTSA_REG 0x94
+#define CEATA_SCR_CAPABILITIES_REG 0x98
+#define CEATA_SCR_CONTROL_REG 0xC0
+
+/* defines for SCR capabilities register bits for ce ata client driver */
+#define CEATA_SCR_CAP_512 0x00000001
+#define CEATA_SCR_CAP_1K 0x00000002
+#define CEATA_SCR_CAP_4K 0x00000004
+
+/* defines CE ATA Control reg bits for ce ata client driver */
+#define CEATA_CNTRL_ENABLE_INTR 0x00
+#define CEATA_CNTRL_DISABLE_INTR 0x02
+#define CEATA_CNTRL_SRST 0x04
+#define CEATA_CNTRL_RSRST 0x00
+
+/* define CE ATA Status reg bits for ce ata client driver */
+#define CEATA_STA_ERROR_BIT 0x01
+#define CEATA_STA_OVR_BIT 0x02
+#define CEATA_STA_SPT_BIT 0x04
+#define CEATA_STA_DRQ_BIT 0x08
+#define CEATA_STA_DRDY_BIT 0x40
+#define CEATA_STA_BSY_BIT 0x80
+
+/* define CE ATA Error reg bits for ce ata client driver */
+#define CEATA_ERROR_ABORTED_BIT 0x04
+#define CEATA_ERROR_IDNF_BIT 0x10
+#define CEATA_ERROR_UNCORRECTABLE_BIT 0x40
+#define CEATA_ERROR_ICRC_BIT 0x80
+
+/* define CE ATA Commands for ce ata client driver */
+#define CEATA_CMD_IDENTIFY_DEVICE 0xEC
+#define CEATA_CMD_READ_DMA_EXT 0x25
+#define CEATA_CMD_WRITE_DMA_EXT 0x35
+#define CEATA_CMD_STANDBY_IMMEDIATE 0xE0
+#define CEATA_CMD_FLUSH_CACHE_EXT 0xEA
+
+struct csd_mmc {
+ uint32_t padding:8;
+ uint32_t structure:2;
+ uint32_t csdSpecVer:4;
+ uint32_t reserved1:2;
+ uint32_t taac:8;
+ uint32_t nsac:8;
+ uint32_t speed:8;
+ uint32_t classes:12;
+ uint32_t rdBlkLen:4;
+ uint32_t rdBlkPartial:1;
+ uint32_t wrBlkMisalign:1;
+ uint32_t rdBlkMisalign:1;
+ uint32_t dsr:1;
+ uint32_t reserved2:2;
+ uint32_t size:12;
+ uint32_t vddRdCurrMin:3;
+ uint32_t vddRdCurrMax:3;
+ uint32_t vddWrCurrMin:3;
+ uint32_t vddWrCurrMax:3;
+ uint32_t devSizeMulti:3;
+ uint32_t eraseGrpSize:5;
+ uint32_t eraseGrpSizeMulti:5;
+ uint32_t wrProtGroupSize:5;
+ uint32_t wrProtGroupEnable:1;
+ uint32_t manuDefEcc:2;
+ uint32_t wrSpeedFactor:3;
+ uint32_t wrBlkLen:4;
+ uint32_t wrBlkPartial:1;
+ uint32_t reserved5:4;
+ uint32_t protAppl:1;
+ uint32_t fileFormatGrp:1;
+ uint32_t copyFlag:1;
+ uint32_t permWrProt:1;
+ uint32_t tmpWrProt:1;
+ uint32_t fileFormat:2;
+ uint32_t eccCode:2;
+};
+
+/* CSD register*/
+union sd_csd {
+ uint32_t csd[4];
+ struct csd_mmc mmc;
+};
+
+struct sd_card_data {
+ union sd_csd csd;
+};
+#endif /* CSL_SD_PROT_H */
diff --git a/include/drivers/brcm/emmc/emmc_pboot_hal_memory_drv.h b/include/drivers/brcm/emmc/emmc_pboot_hal_memory_drv.h
new file mode 100644
index 0000000000..8e61b51c02
--- /dev/null
+++ b/include/drivers/brcm/emmc/emmc_pboot_hal_memory_drv.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2016 - 2020, Broadcom
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PBOOT_HAL_MEMORY_EMMC_DRV_H
+#define PBOOT_HAL_MEMORY_EMMC_DRV_H
+
+#include <drivers/delay_timer.h>
+
+#include "emmc_chal_types.h"
+#include "emmc_chal_sd.h"
+#include "emmc_csl_sdprot.h"
+#include "emmc_csl_sdcmd.h"
+#include "emmc_csl_sd.h"
+#include "emmc_brcm_rdb_sd4_top.h"
+
+#define CLK_SDIO_DIV_52MHZ 0x0
+#define SYSCFG_IOCR4_PAD_10MA 0x38000000
+
+#define SDCLK_CNT_PER_MS 52000
+#define BOOT_ACK_TIMEOUT (50 * SDCLK_CNT_PER_MS)
+#define BOOT_DATA_TIMEOUT (1000 * SDCLK_CNT_PER_MS)
+
+#define EMMC_BOOT_OK 0
+#define EMMC_BOOT_ERROR 1
+#define EMMC_BOOT_TIMEOUT 2
+#define EMMC_BOOT_INVALIDIMAGE 3
+#define EMMC_BOOT_NO_CARD 4
+
+#define EMMC_USER_AREA 0
+#define EMMC_BOOT_PARTITION1 1
+#define EMMC_BOOT_PARTITION2 2
+#define EMMC_USE_CURRENT_PARTITION 3
+
+#define EMMC_BOOT_PARTITION_SIZE (128*1024)
+#define EMMC_BLOCK_SIZE 512
+#define EMMC_DMA_SIZE (4*1024)
+
+/*
+ * EMMC4.3 definitions
+ * Table 6 EXT_CSD access mode
+ * Access
+ * Bits Access Name Operation
+ * 00 Command Set The command set is changed according to the Cmd Set field of
+ * the argument
+ * 01 Set Bits The bits in the pointed uint8_t are set,
+ * according to the 1 bits in the Value field.
+ * 10 Clear Bits The bits in the pointed uint8_t are cleared,
+ * according to the 1 bits in the Value field.
+ * 11 Write Byte The Value field is written into the pointed uint8_t.
+ */
+
+#define SDIO_HW_EMMC_EXT_CSD_WRITE_BYTE 0X03000000
+
+/* Boot bus width1 BOOT_BUS_WIDTH 1 R/W [177] */
+#define SDIO_HW_EMMC_EXT_CSD_BOOT_BUS_WIDTH_OFFSET 0X00B10000
+
+/* Boot configuration BOOT_CONFIG 1 R/W [179] */
+#define SDIO_HW_EMMC_EXT_CSD_BOOT_CONFIG_OFFSET 0X00B30000
+
+/* Bus width mode BUS_WIDTH 1 WO [183] */
+#define SDIO_HW_EMMC_EXT_CSD_BUS_WIDTH_OFFSET 0X00B70000
+
+/*
+ * Bit 6: BOOT_ACK (non-volatile)
+ * 0x0 : No boot acknowledge sent (default)
+ * 0x1 : Boot acknowledge sent during boot operation
+ * Bit[5:3] : BOOT_PARTITION_ENABLE (non-volatile)
+ * User selects boot data that will be sent to master
+ * 0x0 : Device not boot enabled (default)
+ * 0x1 : Boot partition 1 enabled for boot
+ * 0x2 : Boot partition 2 enabled for boot
+ * 0x3-0x6 : Reserved
+ * 0x7 : User area enabled for boot
+ * Bit[2:0] : BOOT_PARTITION_ACCESS
+ * User selects boot partition for read and write operation
+ * 0x0 : No access to boot partition (default)
+ * 0x1 : R/W boot partition 1
+ * 0x2 : R/W boot partition 2
+ * 0x3-0x7 : Reserved
+ */
+
+#define SDIO_HW_EMMC_EXT_CSD_BOOT_ACC_BOOT1 0X00000100
+#define SDIO_HW_EMMC_EXT_CSD_BOOT_ACC_BOOT2 0X00000200
+#define SDIO_HW_EMMC_EXT_CSD_BOOT_ACC_USER 0X00000000
+#define SDIO_HW_EMMC_EXT_CSD_BOOT_EN_BOOT1 0X00004800
+#define SDIO_HW_EMMC_EXT_CSD_BOOT_EN_BOOT2 0X00005000
+#define SDIO_HW_EMMC_EXT_CSD_BOOT_EN_USER 0X00007800
+
+#define SD_US_DELAY(x) udelay(x)
+
+#endif