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authorMadhukar Pappireddy <madhukar.pappireddy@arm.com>2020-06-22 19:57:52 +0000
committerTrustedFirmware Code Review <review@review.trustedfirmware.org>2020-06-22 19:57:52 +0000
commitb667b3696b683bb237f4e90c65b7fe8c4eec3750 (patch)
tree0086fa51afb10908b82f0608a303d02818316618 /include/drivers
parent34dae47b8ed6065d411848d1bffbf6b8406dd685 (diff)
parent5eb16c4717ac08de7c627cb1ee47c3269f0ec363 (diff)
downloadtrusted-firmware-a-b667b3696b683bb237f4e90c65b7fe8c4eec3750.tar.gz
Merge "TF-A GIC driver: Add barrier before eoi" into integration
Diffstat (limited to 'include/drivers')
-rw-r--r--include/drivers/arm/gicv3.h24
1 files changed, 24 insertions, 0 deletions
diff --git a/include/drivers/arm/gicv3.h b/include/drivers/arm/gicv3.h
index 77dc350ddb..97b75b0dae 100644
--- a/include/drivers/arm/gicv3.h
+++ b/include/drivers/arm/gicv3.h
@@ -332,6 +332,18 @@ static inline uint32_t gicv3_get_pending_interrupt_id_sel1(void)
static inline void gicv3_end_of_interrupt_sel1(unsigned int id)
{
+ /*
+ * Interrupt request deassertion from peripheral to GIC happens
+ * by clearing interrupt condition by a write to the peripheral
+ * register. It is desired that the write transfer is complete
+ * before the core tries to change GIC state from 'AP/Active' to
+ * a new state on seeing 'EOI write'.
+ * Since ICC interface writes are not ordered against Device
+ * memory writes, a barrier is required to ensure the ordering.
+ * The dsb will also ensure *completion* of previous writes with
+ * DEVICE nGnRnE attribute.
+ */
+ dsbishst();
write_icc_eoir1_el1(id);
}
@@ -345,6 +357,18 @@ static inline uint32_t gicv3_acknowledge_interrupt(void)
static inline void gicv3_end_of_interrupt(unsigned int id)
{
+ /*
+ * Interrupt request deassertion from peripheral to GIC happens
+ * by clearing interrupt condition by a write to the peripheral
+ * register. It is desired that the write transfer is complete
+ * before the core tries to change GIC state from 'AP/Active' to
+ * a new state on seeing 'EOI write'.
+ * Since ICC interface writes are not ordered against Device
+ * memory writes, a barrier is required to ensure the ordering.
+ * The dsb will also ensure *completion* of previous writes with
+ * DEVICE nGnRnE attribute.
+ */
+ dsbishst();
return write_icc_eoir0_el1(id);
}