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authorEtienne Carriere <etienne.carriere@st.com>2019-12-08 08:20:12 +0100
committerEtienne Carriere <etienne.carriere@st.com>2020-05-11 15:01:29 +0200
commit8fbcd9e421e2b7854928e92ccf11a0542cf186bb (patch)
tree10f7e3dae138ccd1677a7adf72225b7a6ef135ef /include/drivers
parent4e2887f2da05dc510e9ce1e9d648ef2b5d745649 (diff)
downloadtrusted-firmware-a-8fbcd9e421e2b7854928e92ccf11a0542cf186bb.tar.gz
drivers: stm32mp1 clocks: allow tree lookup for several system clocks
Oscillators, PLLs and some system clocks can be related straight to a parent clock. Prior this change were only oscillators and few clocks supported by this look up. This changes adds PLLs and other system clocks. This enables for flexible use of clock tree exploration when computing a clock frequency value. Change-Id: I15ec98023a7095e3120a6954de59a4799d92c66b Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Diffstat (limited to 'include/drivers')
-rw-r--r--include/drivers/st/stm32mp1_rcc.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/include/drivers/st/stm32mp1_rcc.h b/include/drivers/st/stm32mp1_rcc.h
index 4b4aac87d6..2ffc3b2bc2 100644
--- a/include/drivers/st/stm32mp1_rcc.h
+++ b/include/drivers/st/stm32mp1_rcc.h
@@ -250,6 +250,8 @@
#define RCC_MPCKSELR_HSE 0x00000001
#define RCC_MPCKSELR_PLL 0x00000002
#define RCC_MPCKSELR_PLL_MPUDIV 0x00000003
+#define RCC_MPCKSELR_MPUSRC_MASK GENMASK(1, 0)
+#define RCC_MPCKSELR_MPUSRC_SHIFT 0
/* Values of RCC_ASSCKSELR register */
#define RCC_ASSCKSELR_HSI 0x00000000
@@ -266,6 +268,8 @@
#define RCC_CPERCKSELR_HSI 0x00000000
#define RCC_CPERCKSELR_CSI 0x00000001
#define RCC_CPERCKSELR_HSE 0x00000002
+#define RCC_CPERCKSELR_PERSRC_MASK GENMASK(1, 0)
+#define RCC_CPERCKSELR_PERSRC_SHIFT 0
/* Used for most of DIVR register: max div for RTC */
#define RCC_DIVR_DIV_MASK GENMASK(5, 0)