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authorKonstantin Porotchkin <kostap@marvell.com>2019-03-31 16:58:11 +0300
committerMarcin Wojtas <mw@semihalf.com>2020-06-19 18:03:29 +0200
commit5a40d70f067b6238159142755e4e5cb27e292045 (patch)
tree36471b2707cd04ade676b5a03df797c982cffa7c /include/drivers
parent85440805d46646871dc9b2934a0a3932b44df7d4 (diff)
downloadtrusted-firmware-a-5a40d70f067b6238159142755e4e5cb27e292045.tar.gz
drivers: marvell: add support for mapping the entire LLC to SRAM
Add llc_sram_enable() and llc_sram_disable() APIs to Marvell cache_lls driver. Add LLC_SRAM definition to Marvell common makefile - disabled by the default. Add description of LLC_SRAM flag to the build documentation. Change-Id: Ib348e09752ce1206d29268ef96c9018b781db182 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Diffstat (limited to 'include/drivers')
-rw-r--r--include/drivers/marvell/cache_llc.h17
1 files changed, 14 insertions, 3 deletions
diff --git a/include/drivers/marvell/cache_llc.h b/include/drivers/marvell/cache_llc.h
index d8eca9fbf3..b326474ee1 100644
--- a/include/drivers/marvell/cache_llc.h
+++ b/include/drivers/marvell/cache_llc.h
@@ -13,17 +13,18 @@
#define CACHE_LLC_H
#define LLC_CTRL(ap) (MVEBU_LLC_BASE(ap) + 0x100)
+#define LLC_SECURE_CTRL(ap) (MVEBU_LLC_BASE(ap) + 0x10C)
#define LLC_SYNC(ap) (MVEBU_LLC_BASE(ap) + 0x700)
#define LLC_BANKED_MNT_AHR(ap) (MVEBU_LLC_BASE(ap) + 0x724)
#define LLC_INV_WAY(ap) (MVEBU_LLC_BASE(ap) + 0x77C)
#define LLC_BLK_ALOC(ap) (MVEBU_LLC_BASE(ap) + 0x78c)
#define LLC_CLEAN_WAY(ap) (MVEBU_LLC_BASE(ap) + 0x7BC)
#define LLC_CLEAN_INV_WAY(ap) (MVEBU_LLC_BASE(ap) + 0x7FC)
-#define LLC_TC0_LOCK(ap) (MVEBU_LLC_BASE(ap) + 0x920)
+#define LLC_TCN_LOCK(ap, tc) (MVEBU_LLC_BASE(ap) + 0x920 + 4 * (tc))
#define MASTER_LLC_CTRL LLC_CTRL(MVEBU_AP0)
#define MASTER_LLC_INV_WAY LLC_INV_WAY(MVEBU_AP0)
-#define MASTER_LLC_TC0_LOCK LLC_TC0_LOCK(MVEBU_AP0)
+#define MASTER_LLC_TC0_LOCK LLC_TCN_LOCK(MVEBU_AP0, 0)
#define LLC_CTRL_EN 1
#define LLC_EXCLUSIVE_EN 0x100
@@ -34,7 +35,13 @@
#define LLC_WAY_MASK ((1 << LLC_WAYS) - 1)
#define LLC_SIZE (1024 * 1024)
#define LLC_WAY_SIZE (LLC_SIZE / LLC_WAYS)
+#define LLC_TC_NUM 15
+#define LLC_BLK_ALOC_WAY_ID(way) ((way) & 0x1f)
+#define LLC_BLK_ALOC_WAY_DATA_DSBL (0x0 << 6)
+#define LLC_BLK_ALOC_WAY_DATA_CLR (0x1 << 6)
+#define LLC_BLK_ALOC_WAY_DATA_SET (0x3 << 6)
+#define LLC_BLK_ALOC_BASE_ADDR(addr) ((addr) & (LLC_WAY_SIZE - 1))
#ifndef __ASSEMBLER__
void llc_cache_sync(int ap_index);
@@ -45,6 +52,10 @@ void llc_disable(int ap_index);
void llc_enable(int ap_index, int excl_mode);
int llc_is_exclusive(int ap_index);
void llc_runtime_enable(int ap_index);
-#endif
+#if LLC_SRAM
+void llc_sram_enable(int ap_index);
+void llc_sram_disable(int ap_index);
+#endif /* LLC_SRAM */
+#endif /* __ASSEMBLY__ */
#endif /* CACHE_LLC_H */