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authorKonstantin Porotchkin <kostap@marvell.com>2019-04-04 10:02:20 +0300
committerManish Pandey <manish.pandey2@arm.com>2020-07-10 10:55:33 +0000
commit506ff4c0c1d850c3fc18959a44c8280c46788734 (patch)
tree56ac6f709e542eda49942d19ab76fb7ddde8c458 /include/drivers
parent0a977b9b8bfc0356830d88e3602e2e5ef4a1ac06 (diff)
downloadtrusted-firmware-a-506ff4c0c1d850c3fc18959a44c8280c46788734.tar.gz
drivers: marvell: Fix the LLC SRAM driver
- Fix the line address macro - LLC invalidate and enable before ways lock for allocation - Add support for limited SRAM size allocation - Add SRAM RW test function Change-Id: I1867ece3047566ddd7931bd7472e1f47fb42c8d4 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Diffstat (limited to 'include/drivers')
-rw-r--r--include/drivers/marvell/cache_llc.h5
1 files changed, 3 insertions, 2 deletions
diff --git a/include/drivers/marvell/cache_llc.h b/include/drivers/marvell/cache_llc.h
index b326474ee1..d6dd65382f 100644
--- a/include/drivers/marvell/cache_llc.h
+++ b/include/drivers/marvell/cache_llc.h
@@ -41,7 +41,7 @@
#define LLC_BLK_ALOC_WAY_DATA_DSBL (0x0 << 6)
#define LLC_BLK_ALOC_WAY_DATA_CLR (0x1 << 6)
#define LLC_BLK_ALOC_WAY_DATA_SET (0x3 << 6)
-#define LLC_BLK_ALOC_BASE_ADDR(addr) ((addr) & (LLC_WAY_SIZE - 1))
+#define LLC_BLK_ALOC_BASE_ADDR(addr) ((addr) & ~(LLC_WAY_SIZE - 1))
#ifndef __ASSEMBLER__
void llc_cache_sync(int ap_index);
@@ -53,8 +53,9 @@ void llc_enable(int ap_index, int excl_mode);
int llc_is_exclusive(int ap_index);
void llc_runtime_enable(int ap_index);
#if LLC_SRAM
-void llc_sram_enable(int ap_index);
+int llc_sram_enable(int ap_index, int size);
void llc_sram_disable(int ap_index);
+int llc_sram_test(int ap_index, int size, char *msg);
#endif /* LLC_SRAM */
#endif /* __ASSEMBLY__ */