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authorAlexei Fedorov <Alexei.Fedorov@arm.com>2019-04-26 12:07:07 +0100
committerSoby Mathew <soby.mathew@arm.com>2019-05-03 09:27:46 +0000
commitccd4d475ea8681464df8a3e7f55e902a0707c7e2 (patch)
tree022f499184ebb6b8dd084ed5fc9cfeca0033b7db /include/drivers/arm
parent8917380a1eba4f7a499a4a51b75a0488a683d2c0 (diff)
downloadtrusted-firmware-a-ccd4d475ea8681464df8a3e7f55e902a0707c7e2.tar.gz
SMMUv3: refactor the driver code
This patch is a preparation for the subsequent changes in SMMUv3 driver. It introduces a new "smmuv3_poll" function and replaces inline functions for accessing SMMU registers with mmio read/write operations. Also the infinite loop for the poll has been replaced with a counter based timeout. Change-Id: I7a0547beb1509601f253e126b1a7a6ab3b0307e7 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
Diffstat (limited to 'include/drivers/arm')
-rw-r--r--include/drivers/arm/smmu_v3.h17
1 files changed, 12 insertions, 5 deletions
diff --git a/include/drivers/arm/smmu_v3.h b/include/drivers/arm/smmu_v3.h
index 33f3d6fcfc..75c9465af7 100644
--- a/include/drivers/arm/smmu_v3.h
+++ b/include/drivers/arm/smmu_v3.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -8,20 +8,27 @@
#define SMMU_V3_H
#include <stdint.h>
-
#include <lib/utils_def.h>
/* SMMUv3 register offsets from device base */
+#define SMMU_GBPA U(0x0044)
#define SMMU_S_IDR1 U(0x8004)
#define SMMU_S_INIT U(0x803c)
+#define SMMU_S_GBPA U(0x8044)
+
+/* SMMU_GBPA register fields */
+#define SMMU_GBPA_UPDATE (1UL << 31)
+#define SMMU_GBPA_ABORT (1UL << 20)
/* SMMU_S_IDR1 register fields */
-#define SMMU_S_IDR1_SECURE_IMPL_SHIFT 31
-#define SMMU_S_IDR1_SECURE_IMPL_MASK U(0x1)
+#define SMMU_S_IDR1_SECURE_IMPL (1UL << 31)
/* SMMU_S_INIT register fields */
-#define SMMU_S_INIT_INV_ALL_MASK U(0x1)
+#define SMMU_S_INIT_INV_ALL (1UL << 0)
+/* SMMU_S_GBPA register fields */
+#define SMMU_S_GBPA_UPDATE (1UL << 31)
+#define SMMU_S_GBPA_ABORT (1UL << 20)
int smmuv3_init(uintptr_t smmu_base);