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authorMikael Olsson <mikael.olsson@arm.com>2021-02-12 17:30:22 +0100
committerManish Pandey <manish.pandey2@arm.com>2021-04-20 15:42:18 +0200
commit76a21174d2a2f1750b13b2680461b6b80a654848 (patch)
tree0bc0b27fa431a31ae7912aaee38debc8c5f48433 /include/drivers/arm
parent5d5fb10f9cfe105fd1e160fdfc8bb77bd7492799 (diff)
downloadtrusted-firmware-a-76a21174d2a2f1750b13b2680461b6b80a654848.tar.gz
Add SiP service to configure Arm Ethos-N NPU
By default the Arm Ethos-N NPU will boot up in secure mode. In this mode the non-secure world cannot access the registers needed to use the NPU. To still allow the non-secure world to use the NPU, a SiP service has been added that can delegate non-secure access to the registers needed to use it. Only the HW_CONFIG for the Arm Juno platform has been updated to include the device tree for the NPU and the platform currently only loads the HW_CONFIG in AArch64 builds. Signed-off-by: Mikael Olsson <mikael.olsson@arm.com> Change-Id: I65dfd864042ed43faae0a259dcf319cbadb5f3d2
Diffstat (limited to 'include/drivers/arm')
-rw-r--r--include/drivers/arm/ethosn.h61
1 files changed, 61 insertions, 0 deletions
diff --git a/include/drivers/arm/ethosn.h b/include/drivers/arm/ethosn.h
new file mode 100644
index 0000000000..6de2abb85f
--- /dev/null
+++ b/include/drivers/arm/ethosn.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef ETHOSN_H
+#define ETHOSN_H
+
+#include <lib/smccc.h>
+
+/* Function numbers */
+#define ETHOSN_FNUM_VERSION U(0x50)
+#define ETHOSN_FNUM_IS_SEC U(0x51)
+#define ETHOSN_FNUM_HARD_RESET U(0x52)
+#define ETHOSN_FNUM_SOFT_RESET U(0x53)
+/* 0x54-0x5F reserved for future use */
+
+/* SMC64 function IDs */
+#define ETHOSN_FID_64(func_num) U(0xC2000000 | func_num)
+#define ETHOSN_FID_VERSION_64 ETHOSN_FID_64(ETHOSN_FNUM_VERSION)
+#define ETHOSN_FID_IS_SEC_64 ETHOSN_FID_64(ETHOSN_FNUM_IS_SEC)
+#define ETHOSN_FID_HARD_RESET_64 ETHOSN_FID_64(ETHOSN_FNUM_HARD_RESET)
+#define ETHOSN_FID_SOFT_RESET_64 ETHOSN_FID_64(ETHOSN_FNUM_SOFT_RESET)
+
+/* SMC32 function IDs */
+#define ETHOSN_FID_32(func_num) U(0x82000000 | func_num)
+#define ETHOSN_FID_VERSION_32 ETHOSN_FID_32(ETHOSN_FNUM_VERSION)
+#define ETHOSN_FID_IS_SEC_32 ETHOSN_FID_32(ETHOSN_FNUM_IS_SEC)
+#define ETHOSN_FID_HARD_RESET_32 ETHOSN_FID_32(ETHOSN_FNUM_HARD_RESET)
+#define ETHOSN_FID_SOFT_RESET_32 ETHOSN_FID_32(ETHOSN_FNUM_SOFT_RESET)
+
+#define ETHOSN_NUM_SMC_CALLS 8
+
+/* Macro to identify function calls */
+#define ETHOSN_FID_MASK U(0xFFF0)
+#define ETHOSN_FID_VALUE U(0x50)
+#define is_ethosn_fid(_fid) (((_fid) & ETHOSN_FID_MASK) == ETHOSN_FID_VALUE)
+
+/* Service version */
+#define ETHOSN_VERSION_MAJOR U(0)
+#define ETHOSN_VERSION_MINOR U(1)
+
+/* Return codes for function calls */
+#define ETHOSN_SUCCESS 0
+#define ETHOSN_NOT_SUPPORTED -1
+/* -2 Reserved for NOT_REQUIRED */
+/* -3 Reserved for INVALID_PARAMETER */
+#define ETHOSN_FAILURE -4
+#define ETHOSN_CORE_IDX_OUT_OF_RANGE -5
+
+uintptr_t ethosn_smc_handler(uint32_t smc_fid,
+ u_register_t core_idx,
+ u_register_t x2,
+ u_register_t x3,
+ u_register_t x4,
+ void *cookie,
+ void *handle,
+ u_register_t flags);
+
+#endif /* ETHOSN_H */