aboutsummaryrefslogtreecommitdiff
path: root/include/common
diff options
context:
space:
mode:
authorAntonio Nino Diaz <antonio.ninodiaz@arm.com>2018-12-17 17:20:57 +0000
committerAntonio Nino Diaz <antonio.ninodiaz@arm.com>2019-01-04 10:43:16 +0000
commitf5478dedf9e096d9539362b38ceb096b940ba3e2 (patch)
tree92245ba2317586b3d52f67989be9622ae545d332 /include/common
parent07146afb1164e42adf068a505f1d3105c4acaff5 (diff)
downloadtrusted-firmware-a-f5478dedf9e096d9539362b38ceb096b940ba3e2.tar.gz
Reorganize architecture-dependent header files
The architecture dependant header files in include/lib/${ARCH} and include/common/${ARCH} have been moved to /include/arch/${ARCH}. Change-Id: I96f30fdb80b191a51448ddf11b1d4a0624c03394 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Diffstat (limited to 'include/common')
-rw-r--r--include/common/aarch32/asm_macros.S192
-rw-r--r--include/common/aarch32/assert_macros.S26
-rw-r--r--include/common/aarch32/console_macros.S84
-rw-r--r--include/common/aarch32/el3_common_macros.S332
-rw-r--r--include/common/aarch64/asm_macros.S195
-rw-r--r--include/common/aarch64/assert_macros.S29
-rw-r--r--include/common/aarch64/console_macros.S88
-rw-r--r--include/common/aarch64/el3_common_macros.S359
8 files changed, 0 insertions, 1305 deletions
diff --git a/include/common/aarch32/asm_macros.S b/include/common/aarch32/asm_macros.S
deleted file mode 100644
index c54f75c2d9..0000000000
--- a/include/common/aarch32/asm_macros.S
+++ /dev/null
@@ -1,192 +0,0 @@
-/*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-#ifndef ASM_MACROS_S
-#define ASM_MACROS_S
-
-#include <arch.h>
-#include <asm_macros_common.S>
-#include <spinlock.h>
-
-/*
- * TLBI instruction with type specifier that implements the workaround for
- * errata 813419 of Cortex-A57.
- */
-#if ERRATA_A57_813419
-#define TLB_INVALIDATE(_reg, _coproc) \
- stcopr _reg, _coproc; \
- dsb ish; \
- stcopr _reg, _coproc
-#else
-#define TLB_INVALIDATE(_reg, _coproc) \
- stcopr _reg, _coproc
-#endif
-
-#define WORD_SIZE 4
-
- /*
- * Co processor register accessors
- */
- .macro ldcopr reg, coproc, opc1, CRn, CRm, opc2
- mrc \coproc, \opc1, \reg, \CRn, \CRm, \opc2
- .endm
-
- .macro ldcopr16 reg1, reg2, coproc, opc1, CRm
- mrrc \coproc, \opc1, \reg1, \reg2, \CRm
- .endm
-
- .macro stcopr reg, coproc, opc1, CRn, CRm, opc2
- mcr \coproc, \opc1, \reg, \CRn, \CRm, \opc2
- .endm
-
- .macro stcopr16 reg1, reg2, coproc, opc1, CRm
- mcrr \coproc, \opc1, \reg1, \reg2, \CRm
- .endm
-
- /* Cache line size helpers */
- .macro dcache_line_size reg, tmp
- ldcopr \tmp, CTR
- ubfx \tmp, \tmp, #CTR_DMINLINE_SHIFT, #CTR_DMINLINE_WIDTH
- mov \reg, #WORD_SIZE
- lsl \reg, \reg, \tmp
- .endm
-
- .macro icache_line_size reg, tmp
- ldcopr \tmp, CTR
- and \tmp, \tmp, #CTR_IMINLINE_MASK
- mov \reg, #WORD_SIZE
- lsl \reg, \reg, \tmp
- .endm
-
- /*
- * Declare the exception vector table, enforcing it is aligned on a
- * 32 byte boundary.
- */
- .macro vector_base label
- .section .vectors, "ax"
- .align 5
- \label:
- .endm
-
- /*
- * This macro calculates the base address of the current CPU's multi
- * processor(MP) stack using the plat_my_core_pos() index, the name of
- * the stack storage and the size of each stack.
- * Out: r0 = physical address of stack base
- * Clobber: r14, r1, r2
- */
- .macro get_my_mp_stack _name, _size
- bl plat_my_core_pos
- ldr r2, =(\_name + \_size)
- mov r1, #\_size
- mla r0, r0, r1, r2
- .endm
-
- /*
- * This macro calculates the base address of a uniprocessor(UP) stack
- * using the name of the stack storage and the size of the stack
- * Out: r0 = physical address of stack base
- */
- .macro get_up_stack _name, _size
- ldr r0, =(\_name + \_size)
- .endm
-
-#if ARM_ARCH_MAJOR == 7 && !defined(ARMV7_SUPPORTS_VIRTUALIZATION)
- /*
- * ARMv7 cores without Virtualization extension do not support the
- * eret instruction.
- */
- .macro eret
- movs pc, lr
- .endm
-#endif
-
-#if (ARM_ARCH_MAJOR == 7)
- /* ARMv7 does not support stl instruction */
- .macro stl _reg, _write_lock
- dmb
- str \_reg, \_write_lock
- dsb
- .endm
-#endif
-
- /*
- * Helper macro to generate the best mov/movw/movt combinations
- * according to the value to be moved.
- */
- .macro mov_imm _reg, _val
- .if ((\_val) & 0xffff0000) == 0
- mov \_reg, #(\_val)
- .else
- movw \_reg, #((\_val) & 0xffff)
- movt \_reg, #((\_val) >> 16)
- .endif
- .endm
-
- /*
- * Macro to mark instances where we're jumping to a function and don't
- * expect a return. To provide the function being jumped to with
- * additional information, we use 'bl' instruction to jump rather than
- * 'b'.
- *
- * Debuggers infer the location of a call from where LR points to, which
- * is usually the instruction after 'bl'. If this macro expansion
- * happens to be the last location in a function, that'll cause the LR
- * to point a location beyond the function, thereby misleading debugger
- * back trace. We therefore insert a 'nop' after the function call for
- * debug builds, unless 'skip_nop' parameter is non-zero.
- */
- .macro no_ret _func:req, skip_nop=0
- bl \_func
-#if DEBUG
- .ifeq \skip_nop
- nop
- .endif
-#endif
- .endm
-
- /*
- * Reserve space for a spin lock in assembly file.
- */
- .macro define_asm_spinlock _name:req
- .align SPINLOCK_ASM_ALIGN
- \_name:
- .space SPINLOCK_ASM_SIZE
- .endm
-
- /*
- * Helper macro to OR the bottom 32 bits of `_val` into `_reg_l`
- * and the top 32 bits of `_val` into `_reg_h`. If either the bottom
- * or top word of `_val` is zero, the corresponding OR operation
- * is skipped.
- */
- .macro orr64_imm _reg_l, _reg_h, _val
- .if (\_val >> 32)
- orr \_reg_h, \_reg_h, #(\_val >> 32)
- .endif
- .if (\_val & 0xffffffff)
- orr \_reg_l, \_reg_l, #(\_val & 0xffffffff)
- .endif
- .endm
-
- /*
- * Helper macro to bitwise-clear bits in `_reg_l` and
- * `_reg_h` given a 64 bit immediate `_val`. The set bits
- * in the bottom word of `_val` dictate which bits from
- * `_reg_l` should be cleared. Similarly, the set bits in
- * the top word of `_val` dictate which bits from `_reg_h`
- * should be cleared. If either the bottom or top word of
- * `_val` is zero, the corresponding BIC operation is skipped.
- */
- .macro bic64_imm _reg_l, _reg_h, _val
- .if (\_val >> 32)
- bic \_reg_h, \_reg_h, #(\_val >> 32)
- .endif
- .if (\_val & 0xffffffff)
- bic \_reg_l, \_reg_l, #(\_val & 0xffffffff)
- .endif
- .endm
-
-#endif /* ASM_MACROS_S */
diff --git a/include/common/aarch32/assert_macros.S b/include/common/aarch32/assert_macros.S
deleted file mode 100644
index ab3a2ebb70..0000000000
--- a/include/common/aarch32/assert_macros.S
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-#ifndef ASSERT_MACROS_S
-#define ASSERT_MACROS_S
-
- /*
- * Assembler macro to enable asm_assert. We assume that the stack is
- * initialized prior to invoking this macro.
- */
-#define ASM_ASSERT(_cc) \
-.ifndef .L_assert_filename ;\
- .pushsection .rodata.str1.1, "aS" ;\
- .L_assert_filename: ;\
- .string __FILE__ ;\
- .popsection ;\
-.endif ;\
- b##_cc 300f ;\
- ldr r0, =.L_assert_filename ;\
- ldr r1, =__LINE__ ;\
- b asm_assert;\
-300:
-
-#endif /* ASSERT_MACROS_S */
diff --git a/include/common/aarch32/console_macros.S b/include/common/aarch32/console_macros.S
deleted file mode 100644
index ba6e7d050b..0000000000
--- a/include/common/aarch32/console_macros.S
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-#ifndef CONSOLE_MACROS_S
-#define CONSOLE_MACROS_S
-
-#include <console.h>
-
-/*
- * This macro encapsulates the common setup that has to be done at the end of
- * a console driver's register function. It will register all of the driver's
- * callbacks in the console_t structure and initialize the flags field (by
- * default consoles are enabled for the "boot" and "crash" states, this can be
- * changed after registration with the console_set_scope() function). It ends
- * with a tail call that will include return to the caller.
- * REQUIRES console_t pointer in x0 and a valid return address in x30.
- */
-/*
- * The USE_FINISH_CONSOLE_REG_2 guard is introduced to allow selection between
- * the 2 variants of the finish_console_register macro and will be removed
- * once the deprecated variant is removed.
- */
-#ifndef USE_FINISH_CONSOLE_REG_2
-#if !ERROR_DEPRECATED
- /* This version of the macro is deprecated. Use the new version */
- .macro finish_console_register _driver
- /*
- * Add these weak definitions so we will automatically write a 0 if the
- * function doesn't exist. I'd rather use .ifdef but that only works if
- * the function was defined (not just declared .global) above this point
- * in the file, which we can't guarantee.
- */
- .weak console_\_driver\()_putc
- .weak console_\_driver\()_getc
- .weak console_\_driver\()_flush
-
- /* Don't use adrp on weak funcs! See GNU ld bugzilla issue 22589. */
- ldr r1, =console_\_driver\()_putc
- str r1, [r0, #CONSOLE_T_PUTC]
- ldr r1, =console_\_driver\()_getc
- str r1, [r0, #CONSOLE_T_GETC]
- ldr r1, =console_\_driver\()_flush
- str r1, [r0, #CONSOLE_T_FLUSH]
- mov r1, #(CONSOLE_FLAG_BOOT | CONSOLE_FLAG_CRASH)
- str r1, [r0, #CONSOLE_T_FLAGS]
- b console_register
- .endm
-#endif /* ERROR_DEPRECATED */
-#else /* USE_FINISH_CONSOLE_REG_2 */
- /* The new version of the macro not using weak references */
- .macro finish_console_register _driver, putc=0, getc=0, flush=0
- /*
- * If any of the callback is not specified or set as 0, then the
- * corresponding callback entry in console_t is set to 0.
- */
- .ifne \putc
- ldr r1, =console_\_driver\()_putc
- .else
- mov r1, #0
- .endif
- str r1, [r0, #CONSOLE_T_PUTC]
-
- .ifne \getc
- ldr r1, =console_\_driver\()_getc
- .else
- mov r1, #0
- .endif
- str r1, [r0, #CONSOLE_T_GETC]
-
- .ifne \flush
- ldr r1, =console_\_driver\()_flush
- .else
- mov r1, #0
- .endif
- str r1, [r0, #CONSOLE_T_FLUSH]
-
- mov r1, #(CONSOLE_FLAG_BOOT | CONSOLE_FLAG_CRASH)
- str r1, [r0, #CONSOLE_T_FLAGS]
- b console_register
- .endm
-#endif /* USE_FINISH_CONSOLE_REG_2 */
-#endif /* CONSOLE_MACROS_S */
diff --git a/include/common/aarch32/el3_common_macros.S b/include/common/aarch32/el3_common_macros.S
deleted file mode 100644
index 048f16103e..0000000000
--- a/include/common/aarch32/el3_common_macros.S
+++ /dev/null
@@ -1,332 +0,0 @@
-/*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef EL3_COMMON_MACROS_S
-#define EL3_COMMON_MACROS_S
-
-#include <arch.h>
-#include <asm_macros.S>
-#include <assert_macros.S>
-
- /*
- * Helper macro to initialise EL3 registers we care about.
- */
- .macro el3_arch_init_common
- /* ---------------------------------------------------------------------
- * SCTLR has already been initialised - read current value before
- * modifying.
- *
- * SCTLR.I: Enable the instruction cache.
- *
- * SCTLR.A: Enable Alignment fault checking. All instructions that load
- * or store one or more registers have an alignment check that the
- * address being accessed is aligned to the size of the data element(s)
- * being accessed.
- * ---------------------------------------------------------------------
- */
- ldr r1, =(SCTLR_I_BIT | SCTLR_A_BIT)
- ldcopr r0, SCTLR
- orr r0, r0, r1
- stcopr r0, SCTLR
- isb
-
- /* ---------------------------------------------------------------------
- * Initialise SCR, setting all fields rather than relying on the hw.
- *
- * SCR.SIF: Enabled so that Secure state instruction fetches from
- * Non-secure memory are not permitted.
- * ---------------------------------------------------------------------
- */
- ldr r0, =(SCR_RESET_VAL | SCR_SIF_BIT)
- stcopr r0, SCR
-
- /* -----------------------------------------------------
- * Enable the Asynchronous data abort now that the
- * exception vectors have been setup.
- * -----------------------------------------------------
- */
- cpsie a
- isb
-
- /* ---------------------------------------------------------------------
- * Initialise NSACR, setting all the fields, except for the
- * IMPLEMENTATION DEFINED field, rather than relying on the hw. Some
- * fields are architecturally UNKNOWN on reset.
- *
- * NSACR_ENABLE_FP_ACCESS: Represents NSACR.cp11 and NSACR.cp10. The
- * cp11 field is ignored, but is set to same value as cp10. The cp10
- * field is set to allow access to Advanced SIMD and floating point
- * features from both Security states.
- * ---------------------------------------------------------------------
- */
- ldcopr r0, NSACR
- and r0, r0, #NSACR_IMP_DEF_MASK
- orr r0, r0, #(NSACR_RESET_VAL | NSACR_ENABLE_FP_ACCESS)
- stcopr r0, NSACR
- isb
-
- /* ---------------------------------------------------------------------
- * Initialise CPACR, setting all fields rather than relying on hw. Some
- * fields are architecturally UNKNOWN on reset.
- *
- * CPACR.TRCDIS: Trap control for PL0 and PL1 System register accesses
- * to trace registers. Set to zero to allow access.
- *
- * CPACR_ENABLE_FP_ACCESS: Represents CPACR.cp11 and CPACR.cp10. The
- * cp11 field is ignored, but is set to same value as cp10. The cp10
- * field is set to allow full access from PL0 and PL1 to floating-point
- * and Advanced SIMD features.
- * ---------------------------------------------------------------------
- */
- ldr r0, =((CPACR_RESET_VAL | CPACR_ENABLE_FP_ACCESS) & ~(TRCDIS_BIT))
- stcopr r0, CPACR
- isb
-
- /* ---------------------------------------------------------------------
- * Initialise FPEXC, setting all fields rather than relying on hw. Some
- * fields are architecturally UNKNOWN on reset and are set to zero
- * except for field(s) listed below.
- *
- * FPEXC.EN: Enable access to Advanced SIMD and floating point features
- * from all exception levels.
- * ---------------------------------------------------------------------
- */
- ldr r0, =(FPEXC_RESET_VAL | FPEXC_EN_BIT)
- vmsr FPEXC, r0
- isb
-
-#if (ARM_ARCH_MAJOR > 7)
- /* ---------------------------------------------------------------------
- * Initialise SDCR, setting all the fields rather than relying on hw.
- *
- * SDCR.SPD: Disable AArch32 privileged debug. Debug exceptions from
- * Secure EL1 are disabled.
- * ---------------------------------------------------------------------
- */
- ldr r0, =(SDCR_RESET_VAL | SDCR_SPD(SDCR_SPD_DISABLE))
- stcopr r0, SDCR
-#endif
-
- /*
- * If Data Independent Timing (DIT) functionality is implemented,
- * always enable DIT in EL3
- */
- ldcopr r0, ID_PFR0
- and r0, r0, #(ID_PFR0_DIT_MASK << ID_PFR0_DIT_SHIFT)
- cmp r0, #ID_PFR0_DIT_SUPPORTED
- bne 1f
- mrs r0, cpsr
- orr r0, r0, #CPSR_DIT_BIT
- msr cpsr_cxsf, r0
-1:
- .endm
-
-/* -----------------------------------------------------------------------------
- * This is the super set of actions that need to be performed during a cold boot
- * or a warm boot in EL3. This code is shared by BL1 and BL32 (SP_MIN).
- *
- * This macro will always perform reset handling, architectural initialisations
- * and stack setup. The rest of the actions are optional because they might not
- * be needed, depending on the context in which this macro is called. This is
- * why this macro is parameterised ; each parameter allows to enable/disable
- * some actions.
- *
- * _init_sctlr:
- * Whether the macro needs to initialise the SCTLR register including
- * configuring the endianness of data accesses.
- *
- * _warm_boot_mailbox:
- * Whether the macro needs to detect the type of boot (cold/warm). The
- * detection is based on the platform entrypoint address : if it is zero
- * then it is a cold boot, otherwise it is a warm boot. In the latter case,
- * this macro jumps on the platform entrypoint address.
- *
- * _secondary_cold_boot:
- * Whether the macro needs to identify the CPU that is calling it: primary
- * CPU or secondary CPU. The primary CPU will be allowed to carry on with
- * the platform initialisations, while the secondaries will be put in a
- * platform-specific state in the meantime.
- *
- * If the caller knows this macro will only be called by the primary CPU
- * then this parameter can be defined to 0 to skip this step.
- *
- * _init_memory:
- * Whether the macro needs to initialise the memory.
- *
- * _init_c_runtime:
- * Whether the macro needs to initialise the C runtime environment.
- *
- * _exception_vectors:
- * Address of the exception vectors to program in the VBAR_EL3 register.
- * -----------------------------------------------------------------------------
- */
- .macro el3_entrypoint_common \
- _init_sctlr, _warm_boot_mailbox, _secondary_cold_boot, \
- _init_memory, _init_c_runtime, _exception_vectors
-
- /* Make sure we are in Secure Mode */
-#if ENABLE_ASSERTIONS
- ldcopr r0, SCR
- tst r0, #SCR_NS_BIT
- ASM_ASSERT(eq)
-#endif
-
- .if \_init_sctlr
- /* -------------------------------------------------------------
- * This is the initialisation of SCTLR and so must ensure that
- * all fields are explicitly set rather than relying on hw. Some
- * fields reset to an IMPLEMENTATION DEFINED value.
- *
- * SCTLR.TE: Set to zero so that exceptions to an Exception
- * Level executing at PL1 are taken to A32 state.
- *
- * SCTLR.EE: Set the CPU endianness before doing anything that
- * might involve memory reads or writes. Set to zero to select
- * Little Endian.
- *
- * SCTLR.V: Set to zero to select the normal exception vectors
- * with base address held in VBAR.
- *
- * SCTLR.DSSBS: Set to zero to disable speculation store bypass
- * safe behaviour upon exception entry to EL3.
- * -------------------------------------------------------------
- */
- ldr r0, =(SCTLR_RESET_VAL & ~(SCTLR_TE_BIT | SCTLR_EE_BIT | \
- SCTLR_V_BIT | SCTLR_DSSBS_BIT))
- stcopr r0, SCTLR
- isb
- .endif /* _init_sctlr */
-
- /* Switch to monitor mode */
- cps #MODE32_mon
- isb
-
- .if \_warm_boot_mailbox
- /* -------------------------------------------------------------
- * This code will be executed for both warm and cold resets.
- * Now is the time to distinguish between the two.
- * Query the platform entrypoint address and if it is not zero
- * then it means it is a warm boot so jump to this address.
- * -------------------------------------------------------------
- */
- bl plat_get_my_entrypoint
- cmp r0, #0
- bxne r0
- .endif /* _warm_boot_mailbox */
-
- /* ---------------------------------------------------------------------
- * Set the exception vectors (VBAR/MVBAR).
- * ---------------------------------------------------------------------
- */
- ldr r0, =\_exception_vectors
- stcopr r0, VBAR
- stcopr r0, MVBAR
- isb
-
- /* ---------------------------------------------------------------------
- * It is a cold boot.
- * Perform any processor specific actions upon reset e.g. cache, TLB
- * invalidations etc.
- * ---------------------------------------------------------------------
- */
- bl reset_handler
-
- el3_arch_init_common
-
- .if \_secondary_cold_boot
- /* -------------------------------------------------------------
- * Check if this is a primary or secondary CPU cold boot.
- * The primary CPU will set up the platform while the
- * secondaries are placed in a platform-specific state until the
- * primary CPU performs the necessary actions to bring them out
- * of that state and allows entry into the OS.
- * -------------------------------------------------------------
- */
- bl plat_is_my_cpu_primary
- cmp r0, #0
- bne do_primary_cold_boot
-
- /* This is a cold boot on a secondary CPU */
- bl plat_secondary_cold_boot_setup
- /* plat_secondary_cold_boot_setup() is not supposed to return */
- no_ret plat_panic_handler
-
- do_primary_cold_boot:
- .endif /* _secondary_cold_boot */
-
- /* ---------------------------------------------------------------------
- * Initialize memory now. Secondary CPU initialization won't get to this
- * point.
- * ---------------------------------------------------------------------
- */
-
- .if \_init_memory
- bl platform_mem_init
- .endif /* _init_memory */
-
- /* ---------------------------------------------------------------------
- * Init C runtime environment:
- * - Zero-initialise the NOBITS sections. There are 2 of them:
- * - the .bss section;
- * - the coherent memory section (if any).
- * - Relocate the data section from ROM to RAM, if required.
- * ---------------------------------------------------------------------
- */
- .if \_init_c_runtime
-#if defined(IMAGE_BL32) || (defined(IMAGE_BL2) && BL2_AT_EL3)
- /* -----------------------------------------------------------------
- * Invalidate the RW memory used by the image. This
- * includes the data and NOBITS sections. This is done to
- * safeguard against possible corruption of this memory by
- * dirty cache lines in a system cache as a result of use by
- * an earlier boot loader stage.
- * -----------------------------------------------------------------
- */
- ldr r0, =__RW_START__
- ldr r1, =__RW_END__
- sub r1, r1, r0
- bl inv_dcache_range
-#endif
-
- ldr r0, =__BSS_START__
- ldr r1, =__BSS_SIZE__
- bl zeromem
-
-#if USE_COHERENT_MEM
- ldr r0, =__COHERENT_RAM_START__
- ldr r1, =__COHERENT_RAM_UNALIGNED_SIZE__
- bl zeromem
-#endif
-
-#ifdef IMAGE_BL1
- /* -----------------------------------------------------
- * Copy data from ROM to RAM.
- * -----------------------------------------------------
- */
- ldr r0, =__DATA_RAM_START__
- ldr r1, =__DATA_ROM_START__
- ldr r2, =__DATA_SIZE__
- bl memcpy4
-#endif
- .endif /* _init_c_runtime */
-
- /* ---------------------------------------------------------------------
- * Allocate a stack whose memory will be marked as Normal-IS-WBWA when
- * the MMU is enabled. There is no risk of reading stale stack memory
- * after enabling the MMU as only the primary CPU is running at the
- * moment.
- * ---------------------------------------------------------------------
- */
- bl plat_set_my_stack
-
-#if STACK_PROTECTOR_ENABLED
- .if \_init_c_runtime
- bl update_stack_protector_canary
- .endif /* _init_c_runtime */
-#endif
- .endm
-
-#endif /* EL3_COMMON_MACROS_S */
diff --git a/include/common/aarch64/asm_macros.S b/include/common/aarch64/asm_macros.S
deleted file mode 100644
index dea3021377..0000000000
--- a/include/common/aarch64/asm_macros.S
+++ /dev/null
@@ -1,195 +0,0 @@
-/*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-#ifndef ASM_MACROS_S
-#define ASM_MACROS_S
-
-#include <arch.h>
-#include <asm_macros_common.S>
-#include <spinlock.h>
-
-/*
- * TLBI instruction with type specifier that implements the workaround for
- * errata 813419 of Cortex-A57.
- */
-#if ERRATA_A57_813419
-#define TLB_INVALIDATE(_type) \
- tlbi _type; \
- dsb ish; \
- tlbi _type
-#else
-#define TLB_INVALIDATE(_type) \
- tlbi _type
-#endif
-
-
- .macro func_prologue
- stp x29, x30, [sp, #-0x10]!
- mov x29,sp
- .endm
-
- .macro func_epilogue
- ldp x29, x30, [sp], #0x10
- .endm
-
-
- .macro dcache_line_size reg, tmp
- mrs \tmp, ctr_el0
- ubfx \tmp, \tmp, #16, #4
- mov \reg, #4
- lsl \reg, \reg, \tmp
- .endm
-
-
- .macro icache_line_size reg, tmp
- mrs \tmp, ctr_el0
- and \tmp, \tmp, #0xf
- mov \reg, #4
- lsl \reg, \reg, \tmp
- .endm
-
-
- .macro smc_check label
- mrs x0, esr_el3
- ubfx x0, x0, #ESR_EC_SHIFT, #ESR_EC_LENGTH
- cmp x0, #EC_AARCH64_SMC
- b.ne $label
- .endm
-
- /*
- * Declare the exception vector table, enforcing it is aligned on a
- * 2KB boundary, as required by the ARMv8 architecture.
- * Use zero bytes as the fill value to be stored in the padding bytes
- * so that it inserts illegal AArch64 instructions. This increases
- * security, robustness and potentially facilitates debugging.
- */
- .macro vector_base label, section_name=.vectors
- .section \section_name, "ax"
- .align 11, 0
- \label:
- .endm
-
- /*
- * Create an entry in the exception vector table, enforcing it is
- * aligned on a 128-byte boundary, as required by the ARMv8 architecture.
- * Use zero bytes as the fill value to be stored in the padding bytes
- * so that it inserts illegal AArch64 instructions. This increases
- * security, robustness and potentially facilitates debugging.
- */
- .macro vector_entry label, section_name=.vectors
- .cfi_sections .debug_frame
- .section \section_name, "ax"
- .align 7, 0
- .type \label, %function
- .cfi_startproc
- \label:
- .endm
-
- /*
- * Add the bytes until fill the full exception vector, whose size is always
- * 32 instructions. If there are more than 32 instructions in the
- * exception vector then an error is emitted.
- */
- .macro end_vector_entry label
- .cfi_endproc
- .fill \label + (32 * 4) - .
- .endm
-
- /*
- * This macro calculates the base address of the current CPU's MP stack
- * using the plat_my_core_pos() index, the name of the stack storage
- * and the size of each stack
- * Out: X0 = physical address of stack base
- * Clobber: X30, X1, X2
- */
- .macro get_my_mp_stack _name, _size
- bl plat_my_core_pos
- adrp x2, (\_name + \_size)
- add x2, x2, :lo12:(\_name + \_size)
- mov x1, #\_size
- madd x0, x0, x1, x2
- .endm
-
- /*
- * This macro calculates the base address of a UP stack using the
- * name of the stack storage and the size of the stack
- * Out: X0 = physical address of stack base
- */
- .macro get_up_stack _name, _size
- adrp x0, (\_name + \_size)
- add x0, x0, :lo12:(\_name + \_size)
- .endm
-
- /*
- * Helper macro to generate the best mov/movk combinations according
- * the value to be moved. The 16 bits from '_shift' are tested and
- * if not zero, they are moved into '_reg' without affecting
- * other bits.
- */
- .macro _mov_imm16 _reg, _val, _shift
- .if (\_val >> \_shift) & 0xffff
- .if (\_val & (1 << \_shift - 1))
- movk \_reg, (\_val >> \_shift) & 0xffff, LSL \_shift
- .else
- mov \_reg, \_val & (0xffff << \_shift)
- .endif
- .endif
- .endm
-
- /*
- * Helper macro to load arbitrary values into 32 or 64-bit registers
- * which generates the best mov/movk combinations. Many base addresses
- * are 64KB aligned the macro will eliminate updating bits 15:0 in
- * that case
- */
- .macro mov_imm _reg, _val
- .if (\_val) == 0
- mov \_reg, #0
- .else
- _mov_imm16 \_reg, (\_val), 0
- _mov_imm16 \_reg, (\_val), 16
- _mov_imm16 \_reg, (\_val), 32
- _mov_imm16 \_reg, (\_val), 48
- .endif
- .endm
-
- /*
- * Macro to mark instances where we're jumping to a function and don't
- * expect a return. To provide the function being jumped to with
- * additional information, we use 'bl' instruction to jump rather than
- * 'b'.
- *
- * Debuggers infer the location of a call from where LR points to, which
- * is usually the instruction after 'bl'. If this macro expansion
- * happens to be the last location in a function, that'll cause the LR
- * to point a location beyond the function, thereby misleading debugger
- * back trace. We therefore insert a 'nop' after the function call for
- * debug builds, unless 'skip_nop' parameter is non-zero.
- */
- .macro no_ret _func:req, skip_nop=0
- bl \_func
-#if DEBUG
- .ifeq \skip_nop
- nop
- .endif
-#endif
- .endm
-
- /*
- * Reserve space for a spin lock in assembly file.
- */
- .macro define_asm_spinlock _name:req
- .align SPINLOCK_ASM_ALIGN
- \_name:
- .space SPINLOCK_ASM_SIZE
- .endm
-
-#if RAS_EXTENSION
- .macro esb
- .inst 0xd503221f
- .endm
-#endif
-
-#endif /* ASM_MACROS_S */
diff --git a/include/common/aarch64/assert_macros.S b/include/common/aarch64/assert_macros.S
deleted file mode 100644
index 06371c4208..0000000000
--- a/include/common/aarch64/assert_macros.S
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-#ifndef ASSERT_MACROS_S
-#define ASSERT_MACROS_S
-
- /*
- * Assembler macro to enable asm_assert. Use this macro wherever
- * assert is required in assembly. Please note that the macro makes
- * use of label '300' to provide the logic and the caller
- * should make sure that this label is not used to branch prior
- * to calling this macro.
- */
-#define ASM_ASSERT(_cc) \
-.ifndef .L_assert_filename ;\
- .pushsection .rodata.str1.1, "aS" ;\
- .L_assert_filename: ;\
- .string __FILE__ ;\
- .popsection ;\
-.endif ;\
- b._cc 300f ;\
- adr x0, .L_assert_filename ;\
- mov x1, __LINE__ ;\
- b asm_assert ;\
-300:
-
-#endif /* ASSERT_MACROS_S */
diff --git a/include/common/aarch64/console_macros.S b/include/common/aarch64/console_macros.S
deleted file mode 100644
index 5c88d4f229..0000000000
--- a/include/common/aarch64/console_macros.S
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-#ifndef CONSOLE_MACROS_S
-#define CONSOLE_MACROS_S
-
-#include <console.h>
-
-/*
- * This macro encapsulates the common setup that has to be done at the end of
- * a console driver's register function. It will register all of the driver's
- * callbacks in the console_t structure and initialize the flags field (by
- * default consoles are enabled for the "boot" and "crash" states, this can be
- * changed after registration with the console_set_scope() function). It ends
- * with a tail call that will include return to the caller.
- * REQUIRES console_t pointer in x0 and a valid return address in x30.
- */
-/*
- * The USE_FINISH_CONSOLE_REG_2 guard is introduced to allow selection between
- * the 2 variants of the finish_console_register macro and will be removed
- * once the deprecated variant is removed.
- */
-#ifndef USE_FINISH_CONSOLE_REG_2
-#if !ERROR_DEPRECATED
- /* This version of the macro is deprecated. Use the new version */
- .macro finish_console_register _driver
- /*
- * Add these weak definitions so we will automatically write a 0 if the
- * function doesn't exist. I'd rather use .ifdef but that only works if
- * the function was defined (not just declared .global) above this point
- * in the file, which we can't guarantee.
- */
- .weak console_\_driver\()_putc
- .weak console_\_driver\()_getc
- .weak console_\_driver\()_flush
-
- /* Don't use adrp on weak funcs! See GNU ld bugzilla issue 22589. */
- ldr x1, =console_\_driver\()_putc
- str x1, [x0, #CONSOLE_T_PUTC]
- ldr x1, =console_\_driver\()_getc
- str x1, [x0, #CONSOLE_T_GETC]
- ldr x1, =console_\_driver\()_flush
- str x1, [x0, #CONSOLE_T_FLUSH]
- mov x1, #(CONSOLE_FLAG_BOOT | CONSOLE_FLAG_CRASH)
- str x1, [x0, #CONSOLE_T_FLAGS]
- b console_register
- .endm
-#endif /* ERROR_DEPRECATED */
-#else /* USE_FINISH_CONSOLE_REG_2 */
- /* The new version of the macro not using weak references */
- .macro finish_console_register _driver, putc=0, getc=0, flush=0
- /*
- * If any of the callback is not specified or set as 0, then the
- * corresponding callback entry in console_t is set to 0.
- */
- .ifne \putc
- adrp x1, console_\_driver\()_putc
- add x1, x1, :lo12:console_\_driver\()_putc
- str x1, [x0, #CONSOLE_T_PUTC]
- .else
- str xzr, [x0, #CONSOLE_T_PUTC]
- .endif
-
- .ifne \getc
- adrp x1, console_\_driver\()_getc
- add x1, x1, :lo12:console_\_driver\()_getc
- str x1, [x0, #CONSOLE_T_GETC]
- .else
- str xzr, [x0, #CONSOLE_T_GETC]
- .endif
-
- .ifne \flush
- adrp x1, console_\_driver\()_flush
- add x1, x1, :lo12:console_\_driver\()_flush
- str x1, [x0, #CONSOLE_T_FLUSH]
- .else
- str xzr, [x0, #CONSOLE_T_FLUSH]
- .endif
-
- mov x1, #(CONSOLE_FLAG_BOOT | CONSOLE_FLAG_CRASH)
- str x1, [x0, #CONSOLE_T_FLAGS]
- b console_register
- .endm
-#endif /* USE_FINISH_CONSOLE_REG_2 */
-
-#endif /* CONSOLE_MACROS_S */
diff --git a/include/common/aarch64/el3_common_macros.S b/include/common/aarch64/el3_common_macros.S
deleted file mode 100644
index 410aeab75a..0000000000
--- a/include/common/aarch64/el3_common_macros.S
+++ /dev/null
@@ -1,359 +0,0 @@
-/*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef EL3_COMMON_MACROS_S
-#define EL3_COMMON_MACROS_S
-
-#include <arch.h>
-#include <asm_macros.S>
-
- /*
- * Helper macro to initialise EL3 registers we care about.
- */
- .macro el3_arch_init_common
- /* ---------------------------------------------------------------------
- * SCTLR_EL3 has already been initialised - read current value before
- * modifying.
- *
- * SCTLR_EL3.I: Enable the instruction cache.
- *
- * SCTLR_EL3.SA: Enable Stack Alignment check. A SP alignment fault
- * exception is generated if a load or store instruction executed at
- * EL3 uses the SP as the base address and the SP is not aligned to a
- * 16-byte boundary.
- *
- * SCTLR_EL3.A: Enable Alignment fault checking. All instructions that
- * load or store one or more registers have an alignment check that the
- * address being accessed is aligned to the size of the data element(s)
- * being accessed.
- * ---------------------------------------------------------------------
- */
- mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
- mrs x0, sctlr_el3
- orr x0, x0, x1
- msr sctlr_el3, x0
- isb
-
-#ifdef IMAGE_BL31
- /* ---------------------------------------------------------------------
- * Initialise the per-cpu cache pointer to the CPU.
- * This is done early to enable crash reporting to have access to crash
- * stack. Since crash reporting depends on cpu_data to report the
- * unhandled exception, not doing so can lead to recursive exceptions
- * due to a NULL TPIDR_EL3.
- * ---------------------------------------------------------------------
- */
- bl init_cpu_data_ptr
-#endif /* IMAGE_BL31 */
-
- /* ---------------------------------------------------------------------
- * Initialise SCR_EL3, setting all fields rather than relying on hw.
- * All fields are architecturally UNKNOWN on reset. The following fields
- * do not change during the TF lifetime. The remaining fields are set to
- * zero here but are updated ahead of transitioning to a lower EL in the
- * function cm_init_context_common().
- *
- * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at
- * EL2, EL1 and EL0 are not trapped to EL3.
- *
- * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at
- * EL2, EL1 and EL0 are not trapped to EL3.
- *
- * SCR_EL3.SIF: Set to one to disable instruction fetches from
- * Non-secure memory.
- *
- * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from
- * both Security states and both Execution states.
- *
- * SCR_EL3.EA: Set to one to route External Aborts and SError Interrupts
- * to EL3 when executing at any EL.
- *
- * SCR_EL3.{API,APK}: For Armv8.3 pointer authentication feature,
- * disable traps to EL3 when accessing key registers or using pointer
- * authentication instructions from lower ELs.
- * ---------------------------------------------------------------------
- */
- mov_imm x0, ((SCR_RESET_VAL | SCR_EA_BIT | SCR_SIF_BIT | \
- SCR_API_BIT | SCR_APK_BIT) \
- & ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT))
- msr scr_el3, x0
-
- /* ---------------------------------------------------------------------
- * Initialise MDCR_EL3, setting all fields rather than relying on hw.
- * Some fields are architecturally UNKNOWN on reset.
- *
- * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug.
- * Debug exceptions, other than Breakpoint Instruction exceptions, are
- * disabled from all ELs in Secure state.
- *
- * MDCR_EL3.SPD32: Set to 0b10 to disable AArch32 Secure self-hosted
- * privileged debug from S-EL1.
- *
- * MDCR_EL3.TDOSA: Set to zero so that EL2 and EL2 System register
- * access to the powerdown debug registers do not trap to EL3.
- *
- * MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the
- * debug registers, other than those registers that are controlled by
- * MDCR_EL3.TDOSA.
- *
- * MDCR_EL3.TPM: Set to zero so that EL0, EL1, and EL2 System register
- * accesses to all Performance Monitors registers do not trap to EL3.
- * ---------------------------------------------------------------------
- */
- mov_imm x0, ((MDCR_EL3_RESET_VAL | MDCR_SDD_BIT | MDCR_SPD32(MDCR_SPD32_DISABLE)) \
- & ~(MDCR_TDOSA_BIT | MDCR_TDA_BIT | MDCR_TPM_BIT))
- msr mdcr_el3, x0
-
- /* ---------------------------------------------------------------------
- * Enable External Aborts and SError Interrupts now that the exception
- * vectors have been setup.
- * ---------------------------------------------------------------------
- */
- msr daifclr, #DAIF_ABT_BIT
-
- /* ---------------------------------------------------------------------
- * Initialise CPTR_EL3, setting all fields rather than relying on hw.
- * All fields are architecturally UNKNOWN on reset.
- *
- * CPTR_EL3.TCPAC: Set to zero so that any accesses to CPACR_EL1,
- * CPTR_EL2, CPACR, or HCPTR do not trap to EL3.
- *
- * CPTR_EL3.TTA: Set to zero so that System register accesses to the
- * trace registers do not trap to EL3.
- *
- * CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers
- * by Advanced SIMD, floating-point or SVE instructions (if implemented)
- * do not trap to EL3.
- */
- mov_imm x0, (CPTR_EL3_RESET_VAL & ~(TCPAC_BIT | TTA_BIT | TFP_BIT))
- msr cptr_el3, x0
-
- /*
- * If Data Independent Timing (DIT) functionality is implemented,
- * always enable DIT in EL3
- */
- mrs x0, id_aa64pfr0_el1
- ubfx x0, x0, #ID_AA64PFR0_DIT_SHIFT, #ID_AA64PFR0_DIT_LENGTH
- cmp x0, #ID_AA64PFR0_DIT_SUPPORTED
- bne 1f
- mov x0, #DIT_BIT
- msr DIT, x0
-1:
- .endm
-
-/* -----------------------------------------------------------------------------
- * This is the super set of actions that need to be performed during a cold boot
- * or a warm boot in EL3. This code is shared by BL1 and BL31.
- *
- * This macro will always perform reset handling, architectural initialisations
- * and stack setup. The rest of the actions are optional because they might not
- * be needed, depending on the context in which this macro is called. This is
- * why this macro is parameterised ; each parameter allows to enable/disable
- * some actions.
- *
- * _init_sctlr:
- * Whether the macro needs to initialise SCTLR_EL3, including configuring
- * the endianness of data accesses.
- *
- * _warm_boot_mailbox:
- * Whether the macro needs to detect the type of boot (cold/warm). The
- * detection is based on the platform entrypoint address : if it is zero
- * then it is a cold boot, otherwise it is a warm boot. In the latter case,
- * this macro jumps on the platform entrypoint address.
- *
- * _secondary_cold_boot:
- * Whether the macro needs to identify the CPU that is calling it: primary
- * CPU or secondary CPU. The primary CPU will be allowed to carry on with
- * the platform initialisations, while the secondaries will be put in a
- * platform-specific state in the meantime.
- *
- * If the caller knows this macro will only be called by the primary CPU
- * then this parameter can be defined to 0 to skip this step.
- *
- * _init_memory:
- * Whether the macro needs to initialise the memory.
- *
- * _init_c_runtime:
- * Whether the macro needs to initialise the C runtime environment.
- *
- * _exception_vectors:
- * Address of the exception vectors to program in the VBAR_EL3 register.
- * -----------------------------------------------------------------------------
- */
- .macro el3_entrypoint_common \
- _init_sctlr, _warm_boot_mailbox, _secondary_cold_boot, \
- _init_memory, _init_c_runtime, _exception_vectors
-
- .if \_init_sctlr
- /* -------------------------------------------------------------
- * This is the initialisation of SCTLR_EL3 and so must ensure
- * that all fields are explicitly set rather than relying on hw.
- * Some fields reset to an IMPLEMENTATION DEFINED value and
- * others are architecturally UNKNOWN on reset.
- *
- * SCTLR.EE: Set the CPU endianness before doing anything that
- * might involve memory reads or writes. Set to zero to select
- * Little Endian.
- *
- * SCTLR_EL3.WXN: For the EL3 translation regime, this field can
- * force all memory regions that are writeable to be treated as
- * XN (Execute-never). Set to zero so that this control has no
- * effect on memory access permissions.
- *
- * SCTLR_EL3.SA: Set to zero to disable Stack Alignment check.
- *
- * SCTLR_EL3.A: Set to zero to disable Alignment fault checking.
- *
- * SCTLR.DSSBS: Set to zero to disable speculation store bypass
- * safe behaviour upon exception entry to EL3.
- * -------------------------------------------------------------
- */
- mov_imm x0, (SCTLR_RESET_VAL & ~(SCTLR_EE_BIT | SCTLR_WXN_BIT \
- | SCTLR_SA_BIT | SCTLR_A_BIT | SCTLR_DSSBS_BIT))
- msr sctlr_el3, x0
- isb
- .endif /* _init_sctlr */
-
- .if \_warm_boot_mailbox
- /* -------------------------------------------------------------
- * This code will be executed for both warm and cold resets.
- * Now is the time to distinguish between the two.
- * Query the platform entrypoint address and if it is not zero
- * then it means it is a warm boot so jump to this address.
- * -------------------------------------------------------------
- */
- bl plat_get_my_entrypoint
- cbz x0, do_cold_boot
- br x0
-
- do_cold_boot:
- .endif /* _warm_boot_mailbox */
-
- /* ---------------------------------------------------------------------
- * Set the exception vectors.
- * ---------------------------------------------------------------------
- */
- adr x0, \_exception_vectors
- msr vbar_el3, x0
- isb
-
- /* ---------------------------------------------------------------------
- * It is a cold boot.
- * Perform any processor specific actions upon reset e.g. cache, TLB
- * invalidations etc.
- * ---------------------------------------------------------------------
- */
- bl reset_handler
-
- el3_arch_init_common
-
- .if \_secondary_cold_boot
- /* -------------------------------------------------------------
- * Check if this is a primary or secondary CPU cold boot.
- * The primary CPU will set up the platform while the
- * secondaries are placed in a platform-specific state until the
- * primary CPU performs the necessary actions to bring them out
- * of that state and allows entry into the OS.
- * -------------------------------------------------------------
- */
- bl plat_is_my_cpu_primary
- cbnz w0, do_primary_cold_boot
-
- /* This is a cold boot on a secondary CPU */
- bl plat_secondary_cold_boot_setup
- /* plat_secondary_cold_boot_setup() is not supposed to return */
- bl el3_panic
-
- do_primary_cold_boot:
- .endif /* _secondary_cold_boot */
-
- /* ---------------------------------------------------------------------
- * Initialize memory now. Secondary CPU initialization won't get to this
- * point.
- * ---------------------------------------------------------------------
- */
-
- .if \_init_memory
- bl platform_mem_init
- .endif /* _init_memory */
-
- /* ---------------------------------------------------------------------
- * Init C runtime environment:
- * - Zero-initialise the NOBITS sections. There are 2 of them:
- * - the .bss section;
- * - the coherent memory section (if any).
- * - Relocate the data section from ROM to RAM, if required.
- * ---------------------------------------------------------------------
- */
- .if \_init_c_runtime
-#if defined(IMAGE_BL31) || (defined(IMAGE_BL2) && BL2_AT_EL3)
- /* -------------------------------------------------------------
- * Invalidate the RW memory used by the BL31 image. This
- * includes the data and NOBITS sections. This is done to
- * safeguard against possible corruption of this memory by
- * dirty cache lines in a system cache as a result of use by
- * an earlier boot loader stage.
- * -------------------------------------------------------------
- */
- adrp x0, __RW_START__
- add x0, x0, :lo12:__RW_START__
- adrp x1, __RW_END__
- add x1, x1, :lo12:__RW_END__
- sub x1, x1, x0
- bl inv_dcache_range
-#endif
- adrp x0, __BSS_START__
- add x0, x0, :lo12:__BSS_START__
-
- adrp x1, __BSS_END__
- add x1, x1, :lo12:__BSS_END__
- sub x1, x1, x0
- bl zeromem
-
-#if USE_COHERENT_MEM
- adrp x0, __COHERENT_RAM_START__
- add x0, x0, :lo12:__COHERENT_RAM_START__
- adrp x1, __COHERENT_RAM_END_UNALIGNED__
- add x1, x1, :lo12: __COHERENT_RAM_END_UNALIGNED__
- sub x1, x1, x0
- bl zeromem
-#endif
-
-#if defined(IMAGE_BL1) || (defined(IMAGE_BL2) && BL2_IN_XIP_MEM)
- adrp x0, __DATA_RAM_START__
- add x0, x0, :lo12:__DATA_RAM_START__
- adrp x1, __DATA_ROM_START__
- add x1, x1, :lo12:__DATA_ROM_START__
- adrp x2, __DATA_RAM_END__
- add x2, x2, :lo12:__DATA_RAM_END__
- sub x2, x2, x0
- bl memcpy16
-#endif
- .endif /* _init_c_runtime */
-
- /* ---------------------------------------------------------------------
- * Use SP_EL0 for the C runtime stack.
- * ---------------------------------------------------------------------
- */
- msr spsel, #0
-
- /* ---------------------------------------------------------------------
- * Allocate a stack whose memory will be marked as Normal-IS-WBWA when
- * the MMU is enabled. There is no risk of reading stale stack memory
- * after enabling the MMU as only the primary CPU is running at the
- * moment.
- * ---------------------------------------------------------------------
- */
- bl plat_set_my_stack
-
-#if STACK_PROTECTOR_ENABLED
- .if \_init_c_runtime
- bl update_stack_protector_canary
- .endif /* _init_c_runtime */
-#endif
- .endm
-
-#endif /* EL3_COMMON_MACROS_S */