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author | Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> | 2019-08-20 15:33:27 +0800 |
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committer | Soby Mathew <soby.mathew@arm.com> | 2019-09-12 12:36:31 +0000 |
commit | b90f207a1d386ec391bd3ea9eb403c4ad7b7551b (patch) | |
tree | e7e7acdda3c1a7823b8ba8d7f14fe3f27bc1d64f /include/arch | |
parent | 2fc6ffc451c9af16e03eff51e779c33828e9ab07 (diff) | |
download | trusted-firmware-a-b90f207a1d386ec391bd3ea9eb403c4ad7b7551b.tar.gz |
Invalidate dcache build option for bl2 entry at EL3
Some of the platform (ie. Agilex) make use of CCU IPs which will only be
initialized during bl2_el3_early_platform_setup. Any operation to the
cache beforehand will crash the platform. Hence, this will provide an
option to skip the data cache invalidation upon bl2 entry at EL3
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I2c924ed0589a72d0034714c31be8fe57237d1f06
Diffstat (limited to 'include/arch')
-rw-r--r-- | include/arch/aarch64/el3_common_macros.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/include/arch/aarch64/el3_common_macros.S b/include/arch/aarch64/el3_common_macros.S index a36b7da79f..53396d44b6 100644 --- a/include/arch/aarch64/el3_common_macros.S +++ b/include/arch/aarch64/el3_common_macros.S @@ -333,7 +333,7 @@ * --------------------------------------------------------------------- */ .if \_init_c_runtime -#if defined(IMAGE_BL31) || (defined(IMAGE_BL2) && BL2_AT_EL3) +#if defined(IMAGE_BL31) || (defined(IMAGE_BL2) && BL2_AT_EL3 && BL2_INV_DCACHE) /* ------------------------------------------------------------- * Invalidate the RW memory used by the BL31 image. This * includes the data and NOBITS sections. This is done to |