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authorManish V Badarkhe <Manish.Badarkhe@arm.com>2020-07-23 12:43:25 +0100
committerManish V Badarkhe <Manish.Badarkhe@arm.com>2020-08-18 10:49:27 +0100
commit3b8456bd1c9fd2303483f0675786e3fbda81a0af (patch)
treef9667f04051d19ce5cc4bd6585657a3d753e96fe /include/arch
parentcb55615c506d6bff3f1a9223182e190abbbf6fc5 (diff)
downloadtrusted-firmware-a-3b8456bd1c9fd2303483f0675786e3fbda81a0af.tar.gz
runtime_exceptions: Update AT speculative workaround
As per latest mailing communication [1], we decided to update AT speculative workaround implementation in order to disable page table walk for lower ELs(EL1 or EL0) immediately after context switching to EL3 from lower ELs. Previous implementation of AT speculative workaround is available here: 45aecff00 AT speculative workaround is updated as below: 1. Avoid saving and restoring of SCTLR and TCR registers for EL1 in context save and restore routine respectively. 2. On EL3 entry, save SCTLR and TCR registers for EL1. 3. On EL3 entry, update EL1 system registers to disable stage 1 page table walk for lower ELs (EL1 and EL0) and enable EL1 MMU. 4. On EL3 exit, restore SCTLR and TCR registers for EL1 which are saved in step 2. [1]: https://lists.trustedfirmware.org/pipermail/tf-a/2020-July/000586.html Change-Id: Iee8de16f81dc970a8f492726f2ddd57e7bd9ffb5 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Diffstat (limited to 'include/arch')
-rw-r--r--include/arch/aarch64/el3_common_macros.S39
1 files changed, 39 insertions, 0 deletions
diff --git a/include/arch/aarch64/el3_common_macros.S b/include/arch/aarch64/el3_common_macros.S
index 0708de6893..17a4efaf63 100644
--- a/include/arch/aarch64/el3_common_macros.S
+++ b/include/arch/aarch64/el3_common_macros.S
@@ -9,6 +9,7 @@
#include <arch.h>
#include <asm_macros.S>
+#include <context.h>
#include <lib/xlat_tables/xlat_tables_defs.h>
/*
@@ -443,4 +444,42 @@
#endif
.endm
+ .macro apply_at_speculative_wa
+#if ERRATA_SPECULATIVE_AT
+ /*
+ * Explicitly save x30 so as to free up a register and to enable
+ * branching and also, save x29 which will be used in the called
+ * function
+ */
+ stp x29, x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29]
+ bl save_and_update_ptw_el1_sys_regs
+ ldp x29, x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29]
+#endif
+ .endm
+
+ .macro restore_ptw_el1_sys_regs
+#if ERRATA_SPECULATIVE_AT
+ /* -----------------------------------------------------------
+ * In case of ERRATA_SPECULATIVE_AT, must follow below order
+ * to ensure that page table walk is not enabled until
+ * restoration of all EL1 system registers. TCR_EL1 register
+ * should be updated at the end which restores previous page
+ * table walk setting of stage1 i.e.(TCR_EL1.EPDx) bits. ISB
+ * ensures that CPU does below steps in order.
+ *
+ * 1. Ensure all other system registers are written before
+ * updating SCTLR_EL1 using ISB.
+ * 2. Restore SCTLR_EL1 register.
+ * 3. Ensure SCTLR_EL1 written successfully using ISB.
+ * 4. Restore TCR_EL1 register.
+ * -----------------------------------------------------------
+ */
+ isb
+ ldp x28, x29, [sp, #CTX_EL1_SYSREGS_OFFSET + CTX_SCTLR_EL1]
+ msr sctlr_el1, x28
+ isb
+ msr tcr_el1, x29
+#endif
+ .endm
+
#endif /* EL3_COMMON_MACROS_S */