diff options
author | John Powell <john.powell@arm.com> | 2020-03-20 14:21:05 -0500 |
---|---|---|
committer | johpow01 <john.powell@arm.com> | 2020-04-03 16:20:59 -0500 |
commit | 3443a7027d78a9ccebc6940f0a69300ec7c1ed44 (patch) | |
tree | 079c29b2f19a0009fdf7dbe2aa6727f920009a93 /include/arch | |
parent | 0f99bf32df156b7b87454278b049c65221eeeb84 (diff) | |
download | trusted-firmware-a-3443a7027d78a9ccebc6940f0a69300ec7c1ed44.tar.gz |
Fix MISRA C issues in BL1/BL2/BL31
Attempts to address MISRA compliance issues in BL1, BL2, and BL31 code.
Mainly issues like not using boolean expressions in conditionals,
conflicting variable names, ignoring return values without (void), adding
explicit casts, etc.
Change-Id: If1fa18ab621b9c374db73fa6eaa6f6e5e55c146a
Signed-off-by: John Powell <john.powell@arm.com>
Diffstat (limited to 'include/arch')
-rw-r--r-- | include/arch/aarch32/arch.h | 20 | ||||
-rw-r--r-- | include/arch/aarch64/arch.h | 4 |
2 files changed, 14 insertions, 10 deletions
diff --git a/include/arch/aarch32/arch.h b/include/arch/aarch32/arch.h index 20175481f0..8492b3ea4b 100644 --- a/include/arch/aarch32/arch.h +++ b/include/arch/aarch32/arch.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -388,13 +388,17 @@ #define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK) -#define SPSR_MODE32(mode, isa, endian, aif) \ - ((MODE_RW_32 << MODE_RW_SHIFT | \ - ((mode) & MODE32_MASK) << MODE32_SHIFT | \ - ((isa) & SPSR_T_MASK) << SPSR_T_SHIFT | \ - ((endian) & SPSR_E_MASK) << SPSR_E_SHIFT | \ - ((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT) & \ - (~(SPSR_SSBS_BIT))) +#define SPSR_MODE32(mode, isa, endian, aif) \ +( \ + ( \ + (MODE_RW_32 << MODE_RW_SHIFT) | \ + (((mode) & MODE32_MASK) << MODE32_SHIFT) | \ + (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \ + (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \ + (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT) \ + ) & \ + (~(SPSR_SSBS_BIT)) \ +) /* * TTBR definitions diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h index 2b2c11652d..19dd8c5e38 100644 --- a/include/arch/aarch64/arch.h +++ b/include/arch/aarch64/arch.h @@ -264,8 +264,8 @@ (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) -#define SCTLR_EL1_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ - (U(1) << 22) | (U(1) << 20) | (U(1) << 11)) +#define SCTLR_EL1_RES1 ((UL(1) << 29) | (UL(1) << 28) | (UL(1) << 23) | \ + (UL(1) << 22) | (UL(1) << 20) | (UL(1) << 11)) #define SCTLR_AARCH32_EL1_RES1 \ ((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \ (U(1) << 4) | (U(1) << 3)) |