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author | Madhukar Pappireddy <madhukar.pappireddy@arm.com> | 2020-06-02 09:26:30 -0500 |
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committer | Madhukar Pappireddy <madhukar.pappireddy@arm.com> | 2020-06-09 19:01:14 +0000 |
commit | 452d5e5ef11271df6ef8480eed900252fd330f10 (patch) | |
tree | af3ae3d92365d4253cc2bb71572c4ab24e2bdfa8 /fdts | |
parent | 16af48e4cd4d99ccb8818c6f580b8184198ba0fe (diff) | |
download | trusted-firmware-a-452d5e5ef11271df6ef8480eed900252fd330f10.tar.gz |
plat/fvp: Add support for dynamic description of secure interrupts
Using the fconf framework, the Group 0 and Group 1 secure interrupt
descriptors are moved to device tree and retrieved in runtime. This
feature is enabled by the build flag SEC_INT_DESC_IN_FCONF.
Change-Id: I360c63a83286c7ecc2426cd1ff1b4746d61e633c
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
Diffstat (limited to 'fdts')
-rw-r--r-- | fdts/fvp-base-gicv3-psci-common.dtsi | 39 |
1 files changed, 37 insertions, 2 deletions
diff --git a/fdts/fvp-base-gicv3-psci-common.dtsi b/fdts/fvp-base-gicv3-psci-common.dtsi index 0deb8a2e75..192f5748a4 100644 --- a/fdts/fvp-base-gicv3-psci-common.dtsi +++ b/fdts/fvp-base-gicv3-psci-common.dtsi @@ -6,6 +6,11 @@ #include <services/sdei_flags.h> +#define LEVEL 0 +#define EDGE 2 +#define SDEI_NORMAL 0x70 +#define HIGHEST_SEC 0 + /memreserve/ 0x80000000 0x00010000; / { @@ -38,8 +43,9 @@ max-pwr-lvl = <2>; }; -#if SDEI_IN_FCONF +#if SDEI_IN_FCONF || SEC_INT_DESC_IN_FCONF firmware { +#if SDEI_IN_FCONF sdei { compatible = "arm,sdei-1.0"; method = "smc"; @@ -59,9 +65,38 @@ <2001 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>, <2002 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>; }; - }; #endif /* SDEI_IN_FCONF */ +#if SEC_INT_DESC_IN_FCONF + sec_interrupts { + compatible = "arm,secure_interrupt_desc"; + /* Number of G0 and G1 secure interrupts defined by the platform */ + g0_intr_cnt = <2>; + g1s_intr_cnt = <9>; + /* + * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 + * terminology. Each interrupt property descriptor has 3 fields: + * 1. Interrupt number + * 2. Interrupt priority + * 3. Type of interrupt (Edge or Level configured) + */ + g0_intr_desc = < 8 SDEI_NORMAL EDGE>, + <14 HIGHEST_SEC EDGE>; + + g1s_intr_desc = < 9 HIGHEST_SEC EDGE>, + <10 HIGHEST_SEC EDGE>, + <11 HIGHEST_SEC EDGE>, + <12 HIGHEST_SEC EDGE>, + <13 HIGHEST_SEC EDGE>, + <15 HIGHEST_SEC EDGE>, + <29 HIGHEST_SEC LEVEL>, + <56 HIGHEST_SEC LEVEL>, + <57 HIGHEST_SEC LEVEL>; + }; +#endif /* SEC_INT_DESC_IN_FCONF */ + }; +#endif /* SDEI_IN_FCONF || SEC_INT_DESC_IN_FCONF */ + cpus { #address-cells = <2>; #size-cells = <0>; |