diff options
author | Pankaj Gupta <pankaj.gupta@nxp.com> | 2020-12-09 14:02:39 +0530 |
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committer | Pankaj Gupta <pankaj.gupta@nxp.com> | 2021-03-24 09:49:31 +0530 |
commit | d57186ea2cbbfcb7d89b37906e3785cb68fe2fa4 (patch) | |
tree | 64e90d8c8fc2678dcb65758be2d49c329e99efc6 /drivers | |
parent | b35ce0c413a71689a2b46453b9c30596128f13dc (diff) | |
download | trusted-firmware-a-d57186ea2cbbfcb7d89b37906e3785cb68fe2fa4.tar.gz |
nxp: driver pmu for nxp soc
Driver for NXP IP for Power Management Unit.
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I855657eddab357cb182419b188ed8861c46a1b19
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/nxp/pmu/pmu.c | 45 | ||||
-rw-r--r-- | drivers/nxp/pmu/pmu.h | 75 | ||||
-rw-r--r-- | drivers/nxp/pmu/pmu.mk | 28 |
3 files changed, 148 insertions, 0 deletions
diff --git a/drivers/nxp/pmu/pmu.c b/drivers/nxp/pmu/pmu.c new file mode 100644 index 0000000000..2a907c8ce0 --- /dev/null +++ b/drivers/nxp/pmu/pmu.c @@ -0,0 +1,45 @@ +/* + * Copyright 2021 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include <arch.h> +#include <arch_helpers.h> +#include <common/debug.h> +#include <dcfg.h> +#include <lib/mmio.h> +#include <pmu.h> + +void enable_timer_base_to_cluster(uintptr_t nxp_pmu_addr) +{ + uint32_t *cltbenr = NULL; + uint32_t cltbenr_val = 0U; + + cltbenr = (uint32_t *)(nxp_pmu_addr + + CLUST_TIMER_BASE_ENBL_OFFSET); + + cltbenr_val = mmio_read_32((uintptr_t)cltbenr); + + cltbenr_val = cltbenr_val + | (1 << MPIDR_AFFLVL1_VAL(read_mpidr_el1())); + + mmio_write_32((uintptr_t)cltbenr, cltbenr_val); + + VERBOSE("Enable cluster time base\n"); +} + +/* + * Enable core timebase. In certain Layerscape SoCs, the clock for each core's + * has an enable bit in the PMU Physical Core Time Base Enable + * Register (PCTBENR), which allows the watchdog to operate. + */ + +void enable_core_tb(uintptr_t nxp_pmu_addr) +{ + uint32_t *pctbenr = (uint32_t *) (nxp_pmu_addr + + CORE_TIMEBASE_ENBL_OFFSET); + + mmio_write_32((uintptr_t)pctbenr, 0xff); +} diff --git a/drivers/nxp/pmu/pmu.h b/drivers/nxp/pmu/pmu.h new file mode 100644 index 0000000000..28199e852b --- /dev/null +++ b/drivers/nxp/pmu/pmu.h @@ -0,0 +1,75 @@ +/* + * Copyright 2021 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef PMU_H +#define PMU_H + +/* PMU Registers' OFFSET */ +#define PMU_PCPW20SR_OFFSET 0x830 +#define PMU_CLL2FLUSHSETR_OFFSET 0x1110 +#define PMU_CLSL2FLUSHCLRR_OFFSET 0x1114 +#define PMU_CLL2FLUSHSR_OFFSET 0x1118 +#define PMU_POWMGTCSR_VAL (1 << 20) + +/* PMU Registers */ +#define CORE_TIMEBASE_ENBL_OFFSET 0x8A0 +#define CLUST_TIMER_BASE_ENBL_OFFSET 0x18A0 + +#define PMU_IDLE_CLUSTER_MASK 0x2 +#define PMU_FLUSH_CLUSTER_MASK 0x2 +#define PMU_IDLE_CORE_MASK 0xfe + +/* pmu register offsets and bitmaps */ +#define PMU_POWMGTDCR0_OFFSET 0xC20 +#define PMU_POWMGTCSR_OFFSET 0x4000 +#define PMU_CLAINACTSETR_OFFSET 0x1100 +#define PMU_CLAINACTCLRR_OFFSET 0x1104 +#define PMU_CLSINACTSETR_OFFSET 0x1108 +#define PMU_CLSINACTCLRR_OFFSET 0x110C +#define PMU_CLL2FLUSHSETR_OFFSET 0x1110 +#define PMU_CLL2FLUSHCLRR_OFFSET 0x1114 +#define PMU_IPPDEXPCR0_OFFSET 0x4040 +#define PMU_IPPDEXPCR1_OFFSET 0x4044 +#define PMU_IPPDEXPCR2_OFFSET 0x4048 +#define PMU_IPPDEXPCR3_OFFSET 0x404C +#define PMU_IPPDEXPCR4_OFFSET 0x4050 +#define PMU_IPPDEXPCR5_OFFSET 0x4054 +#define PMU_IPPDEXPCR6_OFFSET 0x4058 +#define PMU_IPSTPCR0_OFFSET 0x4120 +#define PMU_IPSTPCR1_OFFSET 0x4124 +#define PMU_IPSTPCR2_OFFSET 0x4128 +#define PMU_IPSTPCR3_OFFSET 0x412C +#define PMU_IPSTPCR4_OFFSET 0x4130 +#define PMU_IPSTPCR5_OFFSET 0x4134 +#define PMU_IPSTPCR6_OFFSET 0x4138 +#define PMU_IPSTPACKSR0_OFFSET 0x4140 +#define PMU_IPSTPACKSR1_OFFSET 0x4144 +#define PMU_IPSTPACKSR2_OFFSET 0x4148 +#define PMU_IPSTPACKSR3_OFFSET 0x414C +#define PMU_IPSTPACKSR4_OFFSET 0x4150 +#define PMU_IPSTPACKSR5_OFFSET 0x4154 +#define PMU_IPSTPACKSR6_OFFSET 0x4158 + +#define CLAINACT_DISABLE_ACP 0xFF +#define CLSINACT_DISABLE_SKY 0xFF +#define POWMGTDCR_STP_OV_EN 0x1 +#define POWMGTCSR_LPM20_REQ 0x00100000 + +/* Used by PMU */ +#define DEVDISR1_MASK 0x024F3504 +#define DEVDISR2_MASK 0x0003FFFF +#define DEVDISR3_MASK 0x0000303F +#define DEVDISR4_MASK 0x0000FFFF +#define DEVDISR5_MASK 0x00F07603 +#define DEVDISR6_MASK 0x00000001 + +#ifndef __ASSEMBLER__ +void enable_timer_base_to_cluster(uintptr_t nxp_pmu_addr); +void enable_core_tb(uintptr_t nxp_pmu_addr); +#endif /* __ASSEMBLER__ */ + +#endif diff --git a/drivers/nxp/pmu/pmu.mk b/drivers/nxp/pmu/pmu.mk new file mode 100644 index 0000000000..56b04229e3 --- /dev/null +++ b/drivers/nxp/pmu/pmu.mk @@ -0,0 +1,28 @@ +# +# Copyright 2021 NXP +# +# SPDX-License-Identifier: BSD-3-Clause +# +#----------------------------------------------------------------------------- +ifeq (${PMU_ADDED},) + +PMU_ADDED := 1 + +PMU_DRIVERS_PATH := ${PLAT_DRIVERS_PATH}/pmu + +PLAT_INCLUDES += -I$(PMU_DRIVERS_PATH) + +PMU_SOURCES += $(PMU_DRIVERS_PATH)/pmu.c + +ifeq (${BL_COMM_PMU_NEEDED},yes) +BL_COMMON_SOURCES += ${PMU_SOURCES} +else +ifeq (${BL2_PMU_NEEDED},yes) +BL2_SOURCES += ${PMU_SOURCES} +endif +ifeq (${BL31_PMU_NEEDED},yes) +BL31_SOURCES += ${PMU_SOURCES} +endif +endif +endif +#------------------------------------------------ |