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authorMadhukar Pappireddy <madhukar.pappireddy@arm.com>2020-10-13 15:46:35 +0000
committerTrustedFirmware Code Review <review@review.trustedfirmware.org>2020-10-13 15:46:35 +0000
commit80d9cf7808429b76ad1dbee064a3eacedd39ab84 (patch)
tree80047c3f30e517a410a5714070cbd4e760544584 /drivers
parent113e8fdab4fd55f3f81febf591f8b44b6e3ac1a2 (diff)
parent6354401276aaf02a671398c8c69a11b9c7ebd80c (diff)
downloadtrusted-firmware-a-80d9cf7808429b76ad1dbee064a3eacedd39ab84.tar.gz
Merge changes from topic "stm32mp1_plat_updates" into integration
* changes: docs: update STM32MP1 with versions details stm32mp1: get peripheral base address from a define stm32mp1: add finished good variant in board identifier
Diffstat (limited to 'drivers')
-rw-r--r--drivers/st/clk/stm32mp1_clk.c37
-rw-r--r--drivers/st/clk/stm32mp_clkfunc.c58
2 files changed, 17 insertions, 78 deletions
diff --git a/drivers/st/clk/stm32mp1_clk.c b/drivers/st/clk/stm32mp1_clk.c
index f8bc5a217a..564bd87989 100644
--- a/drivers/st/clk/stm32mp1_clk.c
+++ b/drivers/st/clk/stm32mp1_clk.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2018-2019, STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2018-2020, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
*/
@@ -1664,28 +1664,26 @@ static void stm32mp1_set_rtcsrc(unsigned int clksrc, bool lse_css)
static void stm32mp1_stgen_config(void)
{
- uintptr_t stgen;
uint32_t cntfid0;
unsigned long rate;
unsigned long long counter;
- stgen = fdt_get_stgen_base();
- cntfid0 = mmio_read_32(stgen + CNTFID_OFF);
+ cntfid0 = mmio_read_32(STGEN_BASE + CNTFID_OFF);
rate = get_clock_rate(stm32mp1_clk_get_parent(STGEN_K));
if (cntfid0 == rate) {
return;
}
- mmio_clrbits_32(stgen + CNTCR_OFF, CNTCR_EN);
- counter = (unsigned long long)mmio_read_32(stgen + CNTCVL_OFF);
- counter |= ((unsigned long long)mmio_read_32(stgen + CNTCVU_OFF)) << 32;
+ mmio_clrbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN);
+ counter = (unsigned long long)mmio_read_32(STGEN_BASE + CNTCVL_OFF);
+ counter |= ((unsigned long long)mmio_read_32(STGEN_BASE + CNTCVU_OFF)) << 32;
counter = (counter * rate / cntfid0);
- mmio_write_32(stgen + CNTCVL_OFF, (uint32_t)counter);
- mmio_write_32(stgen + CNTCVU_OFF, (uint32_t)(counter >> 32));
- mmio_write_32(stgen + CNTFID_OFF, rate);
- mmio_setbits_32(stgen + CNTCR_OFF, CNTCR_EN);
+ mmio_write_32(STGEN_BASE + CNTCVL_OFF, (uint32_t)counter);
+ mmio_write_32(STGEN_BASE + CNTCVU_OFF, (uint32_t)(counter >> 32));
+ mmio_write_32(STGEN_BASE + CNTFID_OFF, rate);
+ mmio_setbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN);
write_cntfrq((u_register_t)rate);
@@ -1695,20 +1693,17 @@ static void stm32mp1_stgen_config(void)
void stm32mp1_stgen_increment(unsigned long long offset_in_ms)
{
- uintptr_t stgen;
unsigned long long cnt;
- stgen = fdt_get_stgen_base();
+ cnt = ((unsigned long long)mmio_read_32(STGEN_BASE + CNTCVU_OFF) << 32) |
+ mmio_read_32(STGEN_BASE + CNTCVL_OFF);
- cnt = ((unsigned long long)mmio_read_32(stgen + CNTCVU_OFF) << 32) |
- mmio_read_32(stgen + CNTCVL_OFF);
+ cnt += (offset_in_ms * mmio_read_32(STGEN_BASE + CNTFID_OFF)) / 1000U;
- cnt += (offset_in_ms * mmio_read_32(stgen + CNTFID_OFF)) / 1000U;
-
- mmio_clrbits_32(stgen + CNTCR_OFF, CNTCR_EN);
- mmio_write_32(stgen + CNTCVL_OFF, (uint32_t)cnt);
- mmio_write_32(stgen + CNTCVU_OFF, (uint32_t)(cnt >> 32));
- mmio_setbits_32(stgen + CNTCR_OFF, CNTCR_EN);
+ mmio_clrbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN);
+ mmio_write_32(STGEN_BASE + CNTCVL_OFF, (uint32_t)cnt);
+ mmio_write_32(STGEN_BASE + CNTCVU_OFF, (uint32_t)(cnt >> 32));
+ mmio_setbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN);
}
static void stm32mp1_pkcs_config(uint32_t pkcs)
diff --git a/drivers/st/clk/stm32mp_clkfunc.c b/drivers/st/clk/stm32mp_clkfunc.c
index e87ab1ba74..8333f6dfbf 100644
--- a/drivers/st/clk/stm32mp_clkfunc.c
+++ b/drivers/st/clk/stm32mp_clkfunc.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2017-2020, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -14,8 +14,6 @@
#include <drivers/st/stm32_gpio.h>
#include <drivers/st/stm32mp_clkfunc.h>
-#define DT_STGEN_COMPAT "st,stm32-stgen"
-
/*
* Get the frequency of an oscillator from its name in device tree.
* @param name: oscillator name
@@ -169,33 +167,6 @@ int fdt_get_rcc_node(void *fdt)
}
/*
- * Get the RCC base address from the device tree
- * @return: RCC address or 0 on error
- */
-uint32_t fdt_rcc_read_addr(void)
-{
- int node;
- void *fdt;
- const fdt32_t *cuint;
-
- if (fdt_get_address(&fdt) == 0) {
- return 0;
- }
-
- node = fdt_get_rcc_node(fdt);
- if (node < 0) {
- return 0;
- }
-
- cuint = fdt_getprop(fdt, node, "reg", NULL);
- if (cuint == NULL) {
- return 0;
- }
-
- return fdt32_to_cpu(*cuint);
-}
-
-/*
* Read a series of parameters in rcc-clk section in device tree
* @param prop_name: Name of the RCC property to be read
* @param array: the array to store the property parameters
@@ -299,33 +270,6 @@ bool fdt_get_rcc_secure_status(void)
}
/*
- * Get the stgen base address.
- * @return: address of stgen on success, and NULL value on failure.
- */
-uintptr_t fdt_get_stgen_base(void)
-{
- int node;
- const fdt32_t *cuint;
- void *fdt;
-
- if (fdt_get_address(&fdt) == 0) {
- return 0;
- }
-
- node = fdt_node_offset_by_compatible(fdt, -1, DT_STGEN_COMPAT);
- if (node < 0) {
- return 0;
- }
-
- cuint = fdt_getprop(fdt, node, "reg", NULL);
- if (cuint == NULL) {
- return 0;
- }
-
- return fdt32_to_cpu(*cuint);
-}
-
-/*
* Get the clock ID of the given node in device tree.
* @param node: node offset
* @return: Clock ID on success, and a negative FDT/ERRNO error code on failure.