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authorPali Rohár <pali@kernel.org>2021-05-13 14:53:44 +0200
committerMarek Behun <marek.behun@nic.cz>2021-05-28 10:13:06 +0100
commit66a7752834382595d26214783ae4698fd1f00bd6 (patch)
tree8ff36976b83ddea3962dfbcf3f0e4af08ee83e98 /drivers
parentc158878249f1bd930906ebd744b90d3f2a8265f1 (diff)
downloadtrusted-firmware-a-66a7752834382595d26214783ae4698fd1f00bd6.tar.gz
fix(plat/marvell/a3720/uart): fix UART clock rate value and divisor calculation
UART parent clock is by default the platform's xtal clock, which is 25 MHz. The value defined in the driver, though, is 25.8048 MHz. This is a hack for the suboptimal divisor calculation Divisor = UART clock / (16 * baudrate) which does not use rounding division, resulting in a suboptimal value for divisor if the correct parent clock rate was used. Change the code for divisor calculation to Divisor = Round(UART clock / (16 * baudrate)) and change the parent clock rate value to 25 MHz. The final UART divisor for default baudrate 115200 is not affected by this change. (Note that the parent clock rate should not be defined via a macro, since the xtal clock can also be 40 MHz. This is outside of the scope of this fix, though.) Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: Iaa401173df87aec94f2dd1b38a90fb6ed0bf0ec6
Diffstat (limited to 'drivers')
-rw-r--r--drivers/marvell/uart/a3700_console.S3
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/marvell/uart/a3700_console.S b/drivers/marvell/uart/a3700_console.S
index b377321898..ad2ccf216d 100644
--- a/drivers/marvell/uart/a3700_console.S
+++ b/drivers/marvell/uart/a3700_console.S
@@ -45,8 +45,9 @@ func console_a3700_core_init
cbz w2, init_fail
/* Program the baudrate */
- /* Divisor = Uart clock / (16 * baudrate) */
+ /* Divisor = Round(Uartclock / (16 * baudrate)) */
lsl w2, w2, #4
+ add w1, w1, w2, lsr #1
udiv w2, w1, w2
and w2, w2, #0x3ff