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authorAlex Leibovich <alexl@marvell.com>2019-02-25 13:13:48 +0200
committerMarcin Wojtas <mw@semihalf.com>2020-06-07 00:06:03 +0200
commit615d859b2e59d3c7f5f218c768340a3a3de0b8dc (patch)
tree7a9fa5b2f40ad84d402b4feed50d5af9c22e5053 /drivers
parent85d2ed150158e4c92f3238342a76dea4c30d7a95 (diff)
downloadtrusted-firmware-a-615d859b2e59d3c7f5f218c768340a3a3de0b8dc.tar.gz
ble: ap807: improve PLL configuration sequence
Update PLL configuration according to HW team guidelines. Change-Id: I23cac4fb4a638e7416965a5399ce6947e08d0711 Signed-off-by: Alex Leibovich <alexl@marvell.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/marvell/ap807_clocks_init.c15
1 files changed, 15 insertions, 0 deletions
diff --git a/drivers/marvell/ap807_clocks_init.c b/drivers/marvell/ap807_clocks_init.c
index d6a97b22bf..c1f8619092 100644
--- a/drivers/marvell/ap807_clocks_init.c
+++ b/drivers/marvell/ap807_clocks_init.c
@@ -39,14 +39,29 @@
#define AP807_CPU_PLL_PARAM(cluster) AP807_CPU_PLL_CTRL(cluster)
#define AP807_CPU_PLL_CFG(cluster) (AP807_CPU_PLL_CTRL(cluster) + 0x4)
#define AP807_CPU_PLL_CFG_BYPASS_MODE (0x1)
+#define AP807_CPU_PLL_FRC_DSCHG (0x2)
#define AP807_CPU_PLL_CFG_USE_REG_FILE (0x1 << 9)
static void pll_set_freq(unsigned int freq_val)
{
int i;
+ if (freq_val != PLL_FREQ_2200)
+ return;
+
for (i = 0 ; i < AP807_CLUSTER_NUM ; i++) {
+ /* Set parameter of cluster i PLL to 2.2GHz */
mmio_write_32(AP807_CPU_PLL_PARAM(i), freq_val);
+ /* Set apll_lpf_frc_dschg - Control
+ * voltage of internal VCO is discharged
+ */
+ mmio_write_32(AP807_CPU_PLL_CFG(i),
+ AP807_CPU_PLL_FRC_DSCHG);
+ /* Set use_rf_conf load PLL parameter from register */
+ mmio_write_32(AP807_CPU_PLL_CFG(i),
+ AP807_CPU_PLL_FRC_DSCHG |
+ AP807_CPU_PLL_CFG_USE_REG_FILE);
+ /* Un-set apll_lpf_frc_dschg */
mmio_write_32(AP807_CPU_PLL_CFG(i),
AP807_CPU_PLL_CFG_USE_REG_FILE);
}