aboutsummaryrefslogtreecommitdiff
path: root/drivers
diff options
context:
space:
mode:
authorPali Rohár <pali@kernel.org>2021-05-14 15:52:11 +0200
committerPali Rohár <pali@kernel.org>2021-06-02 14:19:52 +0100
commit5a91c439cbeb1f64b8b9830de91efad5113d3c89 (patch)
tree331a918c1e5300656a7ad1c766ed2f5d7ebf3471 /drivers
parent3133625859b74df42deddd80b705578af6fc2fea (diff)
downloadtrusted-firmware-a-5a91c439cbeb1f64b8b9830de91efad5113d3c89.tar.gz
fix(plat/marvell/a3720/uart): fix UART parent clock rate determination
The UART code for the A3K platform assumes that UART parent clock rate is always 25 MHz. This is incorrect, because the xtal clock can also run at 40 MHz (this is board specific). The frequency of the xtal clock is determined by a value on a strapping pin during SOC reset. The code to determine this frequency is already in A3K's comphy driver. Move the get_ref_clk() function from the comphy driver to a separate file and use it for UART parent clock rate determination. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I8bb18a2d020ef18fe65aa06ffa4ab205c71be92e
Diffstat (limited to 'drivers')
-rw-r--r--drivers/marvell/comphy/phy-comphy-3700.c24
1 files changed, 1 insertions, 23 deletions
diff --git a/drivers/marvell/comphy/phy-comphy-3700.c b/drivers/marvell/comphy/phy-comphy-3700.c
index 02fe97c2ad..7377e5e3d9 100644
--- a/drivers/marvell/comphy/phy-comphy-3700.c
+++ b/drivers/marvell/comphy/phy-comphy-3700.c
@@ -14,6 +14,7 @@
#include <mvebu.h>
#include <mvebu_def.h>
+#include <plat_marvell.h>
#include "phy-comphy-3700.h"
#include "phy-comphy-common.h"
@@ -29,15 +30,6 @@
#define USB3_GBE1_PHY (MVEBU_REGS_BASE + 0x5C000)
#define COMPHY_SD_ADDR (MVEBU_REGS_BASE + 0x1F000)
-/*
- * Below address in used only for reading, therefore no problem with concurrent
- * Linux access.
- */
-#define MVEBU_TEST_PIN_LATCH_N (MVEBU_NB_GPIO_REG_BASE + 0x8)
- #define MVEBU_XTAL_MODE_MASK BIT(9)
- #define MVEBU_XTAL_MODE_OFFS 9
- #define MVEBU_XTAL_CLOCK_25MHZ 0x0
-
struct sgmii_phy_init_data_fix {
uint16_t addr;
uint16_t value;
@@ -125,20 +117,6 @@ static uint16_t sgmii_phy_init[512] = {
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 /*1F8 */
};
-/* returns reference clock in MHz (25 or 40) */
-static uint32_t get_ref_clk(void)
-{
- uint32_t val;
-
- val = (mmio_read_32(MVEBU_TEST_PIN_LATCH_N) & MVEBU_XTAL_MODE_MASK) >>
- MVEBU_XTAL_MODE_OFFS;
-
- if (val == MVEBU_XTAL_CLOCK_25MHZ)
- return 25;
- else
- return 40;
-}
-
/* PHY selector configures with corresponding modes */
static void mvebu_a3700_comphy_set_phy_selector(uint8_t comphy_index,
uint32_t comphy_mode)