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authorMing Huang <huangming@linux.alibaba.com>2021-06-04 16:23:22 +0800
committerMing Huang <huangming@linux.alibaba.com>2021-07-23 10:48:00 +0800
commit5a5e0aac398989536dc4be790820af89da3d093a (patch)
tree8bd27563aeb13f3baeee3b9fa00fac9298254371 /drivers
parentc791113776c91e13c930d7b3e1081a3902e4c856 (diff)
downloadtrusted-firmware-a-5a5e0aac398989536dc4be790820af89da3d093a.tar.gz
fix(gicv3): add dsb in both disable and enable function of gicv3_cpuif
A RAS error may be triggered while offline core in OS. Error: Uncorrected software error in the Distributor, with IERR=9,SERR=f. Core put to sleep before its Group enables were cleared. gicv3_cpuif_disable() will be called in offline core flow. According to GIC architecture version 3 and version 4: Architectural execution of a DSB instruction guarantees that the last value written to ICC_IGRPEN0_EL1, ICC_IGRPEN1_EL1, ICC_IGRPEN1_EL3 or GICC_CTLR.{EnableGrp0, EnableGrp1}is observed by the associated Redistributor. An ISB or other context synchronization operation must precede the DSB to ensure visibility of System register writes. Signed-off-by: Ming Huang <huangming@linux.alibaba.com> Change-Id: Iff1475657f401374c761b5e8f2f5b3a4b2040e9d
Diffstat (limited to 'drivers')
-rw-r--r--drivers/arm/gic/v3/gicv3_main.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/arm/gic/v3/gicv3_main.c b/drivers/arm/gic/v3/gicv3_main.c
index 668416cb59..b1139b5e97 100644
--- a/drivers/arm/gic/v3/gicv3_main.c
+++ b/drivers/arm/gic/v3/gicv3_main.c
@@ -332,6 +332,8 @@ void gicv3_cpuif_enable(unsigned int proc_num)
write_icc_igrpen1_el3(read_icc_igrpen1_el3() |
IGRPEN1_EL3_ENABLE_G1S_BIT);
isb();
+ /* Add DSB to ensure visibility of System register writes */
+ dsb();
}
/*******************************************************************************
@@ -363,6 +365,8 @@ void gicv3_cpuif_disable(unsigned int proc_num)
/* Synchronise accesses to group enable registers */
isb();
+ /* Add DSB to ensure visibility of System register writes */
+ dsb();
/* Mark the connected core as asleep */
gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];