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author | Hiroyuki Nakano <hiroyuki.nakano.cj@renesas.com> | 2019-05-16 09:21:37 +0900 |
---|---|---|
committer | Marek Vasut <marek.vasut+renesas@gmail.com> | 2019-07-12 06:38:10 +0200 |
commit | 4b5c1f3060be49722be38d52dfa4f3207d270b6c (patch) | |
tree | fa76773f6a68b96ae8c1cbe1c29e27c9f1bf8c9c /drivers/staging | |
parent | 274e8714ed32c2c69e7173eafa7c050fe67258b0 (diff) | |
download | trusted-firmware-a-4b5c1f3060be49722be38d52dfa4f3207d270b6c.tar.gz |
rcar_gen3: drivers: ddr-a: Update E3 DDR setting
[IPL/DDR]
- Update E3 DDR setting rev.0.12.
Signed-off-by: Hiroyuki Nakano <hiroyuki.nakano.cj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Ic9fb7ed1cd7588fab169a99c4070a8dfc40038dc
Diffstat (limited to 'drivers/staging')
-rw-r--r-- | drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c | 12 | ||||
-rw-r--r-- | drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.h | 4 |
2 files changed, 4 insertions, 12 deletions
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c index c289c88fd8..544cadc83f 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c +++ b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -100,12 +100,8 @@ uint32_t init_ddr(void) #if RCAR_DRAM_DDR3L_MEMCONF == 0 WriteReg_32(DBSC_E3_DBMEMCONF00, 0x0f030a02); /* 1GB */ -#elif RCAR_DRAM_DDR3L_MEMCONF == 1 - WriteReg_32(DBSC_E3_DBMEMCONF00, 0x10030a02); /* 2GB(default) */ -#elif RCAR_DRAM_DDR3L_MEMCONF == 2 - WriteReg_32(DBSC_E3_DBMEMCONF00, 0x10030b02); /* 4GB */ #else - WriteReg_32(DBSC_E3_DBMEMCONF00, 0x10030a02); /* 2GB */ + WriteReg_32(DBSC_E3_DBMEMCONF00, 0x10030a02); /* 2GB(default) */ #endif #if RCAR_DRAM_DDR3L_MEMDUAL == 1 @@ -894,10 +890,6 @@ uint32_t recovery_from_backup_mode(void) #if RCAR_DRAM_DDR3L_MEMCONF == 0 WriteReg_32(DBSC_E3_DBMEMCONF00, 0x0f030a02); -#elif RCAR_DRAM_DDR3L_MEMCONF == 1 - WriteReg_32(DBSC_E3_DBMEMCONF00, 0x10030a02); -#elif RCAR_DRAM_DDR3L_MEMCONF == 2 - WriteReg_32(DBSC_E3_DBMEMCONF00, 0x10030b02); #else WriteReg_32(DBSC_E3_DBMEMCONF00, 0x10030a02); #endif diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.h b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.h index 2e9a5bfc11..1a96a69c7c 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.h +++ b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,7 +9,7 @@ #include <stdint.h> -#define RCAR_E3_DDR_VERSION "rev.0.11" +#define RCAR_E3_DDR_VERSION "rev.0.12" #ifdef ddr_qos_init_setting #define REFRESH_RATE 3900 /* Average periodic refresh interval[ns]. Support 3900,7800 */ |