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authorBiju Das <biju.das.jz@bp.renesas.com>2020-12-16 11:15:33 +0000
committerBiju Das <biju.das.jz@bp.renesas.com>2021-01-13 13:03:49 +0000
commitf1be079225fa57bc348baf8163847d8b6b5c5a9d (patch)
tree94142c2b255d3bb79e82885f2e7119b218abc9df /drivers/renesas/common/rpc/rpc_driver.c
parentb50b6c8149bf33b2001a228aed68fd1dd468b7ba (diff)
downloadtrusted-firmware-a-f1be079225fa57bc348baf8163847d8b6b5c5a9d.tar.gz
drivers: renesas: rpc: Move to common
Move rpc driver code to common directory, so that the same code can be re-used by both R-Car Gen3 and RZ/G2 platforms. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Change-Id: I04805d720d95b8edcc14e652f897fadc7f432197
Diffstat (limited to 'drivers/renesas/common/rpc/rpc_driver.c')
-rw-r--r--drivers/renesas/common/rpc/rpc_driver.c57
1 files changed, 57 insertions, 0 deletions
diff --git a/drivers/renesas/common/rpc/rpc_driver.c b/drivers/renesas/common/rpc/rpc_driver.c
new file mode 100644
index 0000000000..63de5b851a
--- /dev/null
+++ b/drivers/renesas/common/rpc/rpc_driver.c
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+#include <string.h>
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+
+#include "cpg_registers.h"
+#include "rcar_def.h"
+#include "rcar_private.h"
+#include "rpc_registers.h"
+
+#define MSTPSR9_RPC_BIT (0x00020000U)
+#define RPC_CMNCR_MD_BIT (0x80000000U)
+#define RPC_PHYCNT_CAL BIT(31)
+#define RPC_PHYCNT_STRTIM_M3V1 (0x6 << 15UL)
+#define RPC_PHYCNT_STRTIM (0x7 << 15UL)
+
+static void rpc_enable(void)
+{
+ /* Enable clock supply to RPC. */
+ mstpcr_write(CPG_SMSTPCR9, CPG_MSTPSR9, MSTPSR9_RPC_BIT);
+}
+
+static void rpc_setup(void)
+{
+ uint32_t product, cut, reg, phy_strtim;
+
+ if (mmio_read_32(RPC_CMNCR) & RPC_CMNCR_MD_BIT)
+ mmio_clrbits_32(RPC_CMNCR, RPC_CMNCR_MD_BIT);
+
+ product = mmio_read_32(RCAR_PRR) & PRR_PRODUCT_MASK;
+ cut = mmio_read_32(RCAR_PRR) & PRR_CUT_MASK;
+
+ if ((product == PRR_PRODUCT_M3) && (cut < PRR_PRODUCT_30))
+ phy_strtim = RPC_PHYCNT_STRTIM_M3V1;
+ else
+ phy_strtim = RPC_PHYCNT_STRTIM;
+
+ reg = mmio_read_32(RPC_PHYCNT);
+ reg &= ~RPC_PHYCNT_STRTIM;
+ reg |= phy_strtim;
+ mmio_write_32(RPC_PHYCNT, reg);
+ reg |= RPC_PHYCNT_CAL;
+ mmio_write_32(RPC_PHYCNT, reg);
+}
+
+void rcar_rpc_init(void)
+{
+ rpc_enable();
+ rpc_setup();
+}