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authorjohpow01 <john.powell@arm.com>2020-06-03 15:23:31 -0500
committerJohn Powell <john.powell@arm.com>2020-06-25 14:50:58 +0000
commit62bbfe82c8b29834e9f278bc6eefdf386c39aecd (patch)
tree079a7a69ec6b5f9dc78cb5e2216a7ecb097cb869 /docs
parentc275ea1883d6a3a0d5187ca2e2ad4705385fe722 (diff)
downloadtrusted-firmware-a-62bbfe82c8b29834e9f278bc6eefdf386c39aecd.tar.gz
Workaround for Cortex A77 erratum 1800714
Cortex A77 erratum 1800714 is a Cat B erratum, present in older revisions of the Cortex A77 processor core. The workaround is to set a bit in the ECTLR_EL1 system register, which disables allocation of splintered pages in the L2 TLB. Since this is the first errata workaround implemented for Cortex A77, this patch also adds the required cortex_a77_reset_func in the file lib/cpus/aarch64/cortex_a77.S. This errata is explained in this SDEN: https://static.docs.arm.com/101992/0010/Arm_Cortex_A77_MP074_Software_Developer_Errata_Notice_v10.pdf Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I844de34ee1bd0268f80794e2d9542de2f30fd3ad
Diffstat (limited to 'docs')
-rw-r--r--docs/design/cpu-specific-build-macros.rst5
1 files changed, 5 insertions, 0 deletions
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index 264d0c6883..6b6c639336 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -233,6 +233,11 @@ For Cortex-A76, the following errata build flags are defined :
- ``ERRATA_A76_1800710``: This applies errata 1800710 workaround to Cortex-A76
CPU. This needs to be enabled only for revision <= r4p0 of the CPU.
+For Cortex-A77, the following errata build flags are defined :
+
+- ``ERRATA_A77_1800714``: This applies errata 1800714 workaround to Cortex-A77
+ CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
+
For Cortex-A78, the following errata build flags are defined :
- ``ERRATA_A78_1688305``: This applies errata 1688305 workaround to Cortex-A78