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authorJimmy Brisson <jimmy.brisson@arm.com>2020-06-01 10:18:22 -0500
committerJimmy Brisson <jimmy.brisson@arm.com>2020-06-01 17:33:22 -0500
commit3f35709c55e1c27f60389ef1b43a2b436d3d4eb7 (patch)
tree3aa2e8bffe98d86980cbe2de78f2017f25f9ead9 /docs
parent83c1584dcbaeca03a16ce36af828468b5704c10c (diff)
downloadtrusted-firmware-a-3f35709c55e1c27f60389ef1b43a2b436d3d4eb7.tar.gz
Rename Cortex-Hercules to Cortex-A78
Change-Id: I89b90cbdfc8f2aa898b4f3676a4764f060f8e138 Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
Diffstat (limited to 'docs')
-rw-r--r--docs/design/cpu-specific-build-macros.rst9
1 files changed, 4 insertions, 5 deletions
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index 258f73d0b7..591f2f886f 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -227,11 +227,10 @@ For Cortex-A76, the following errata build flags are defined :
- ``ERRATA_A76_1275112``: This applies errata 1275112 workaround to Cortex-A76
CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
-For Hercules, the following errata build flags are defined :
+For Cortex-A78, the following errata build flags are defined :
-- ``ERRATA_HERCULES_1688305``: This applies errata 1688305 workaround to
- Hercules CPU. This needs to be enabled only for revision r0p0 - r1p0 of
- the CPU.
+- ``ERRATA_A78_1688305``: This applies errata 1688305 workaround to Cortex-A78
+ CPU. This needs to be enabled only for revision r0p0 - r1p0 of the CPU.
For Neoverse N1, the following errata build flags are defined :
@@ -338,7 +337,7 @@ architecture that can be enabled by the platform as desired.
--------------
-*Copyright (c) 2014-2019, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2014-2020, Arm Limited and Contributors. All rights reserved.*
.. _CVE-2017-5715: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-5715
.. _CVE-2018-3639: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2018-3639