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authordanh-arm <dan.handley@arm.com>2017-08-30 14:34:57 +0100
committerGitHub <noreply@github.com>2017-08-30 14:34:57 +0100
commitb15bab6bbc91b4a168717391c25c478de2629baf (patch)
treef4fdbd959ee45b55346250170873c1ba4bcd04fa /docs/firmware-design.rst
parent1b05282abfbcef65825310cfe9f32bfe2bf81a2f (diff)
parent9fce2725a4c863983f09ba71289f00931c156202 (diff)
downloadtrusted-firmware-a-b15bab6bbc91b4a168717391c25c478de2629baf.tar.gz
Merge pull request #1066 from islmit01/im/enable_cnp_bit
Enable CnP bit for ARMv8.2 CPUs
Diffstat (limited to 'docs/firmware-design.rst')
-rw-r--r--docs/firmware-design.rst11
1 files changed, 11 insertions, 0 deletions
diff --git a/docs/firmware-design.rst b/docs/firmware-design.rst
index 36038ad6d6..997d29b879 100644
--- a/docs/firmware-design.rst
+++ b/docs/firmware-design.rst
@@ -2366,6 +2366,17 @@ This Architecture Extension is targeted when ``ARM_ARCH_MAJOR`` >= 8, or when
- The Compare and Swap instruction is used to implement spinlocks. Otherwise,
the load-/store-exclusive instruction pair is used.
+ARMv8.2
+~~~~~~~
+
+This Architecture Extension is targeted when ``ARM_ARCH_MAJOR`` == 8 and
+``ARM_ARCH_MINOR`` >= 2.
+
+- The Common not Private (CnP) bit is enabled to indicate that multiple
+ Page Entries in the same Inner Shareable domain use the same translation
+ table entries for a given stage of translation for a particular translation
+ regime.
+
Code Structure
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