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authorIsla Mitchell <isla.mitchell@arm.com>2017-08-07 11:20:13 +0100
committerIsla Mitchell <isla.mitchell@arm.com>2017-08-24 17:23:43 +0100
commit9fce2725a4c863983f09ba71289f00931c156202 (patch)
tree3601fa7dd5efed787ea701a2e10a4e9313e85755 /docs/firmware-design.rst
parentf45e232ab9c93c22c1cffa2ee4c17f34d808b918 (diff)
downloadtrusted-firmware-a-9fce2725a4c863983f09ba71289f00931c156202.tar.gz
Enable CnP bit for ARMv8.2 CPUs
This patch enables the CnP (Common not Private) bit for secure page tables so that multiple PEs in the same Inner Shareable domain can use the same translation table entries for a given stage of translation in a particular translation regime. This only takes effect when ARM Trusted Firmware is built with ARM_ARCH_MINOR >= 2. ARM Trusted Firmware Design has been updated to include a description of this feature usage. Change-Id: I698305f047400119aa1900d34c65368022e410b8 Signed-off-by: Isla Mitchell <isla.mitchell@arm.com>
Diffstat (limited to 'docs/firmware-design.rst')
-rw-r--r--docs/firmware-design.rst11
1 files changed, 11 insertions, 0 deletions
diff --git a/docs/firmware-design.rst b/docs/firmware-design.rst
index 4c3c4204e7..facf0166c0 100644
--- a/docs/firmware-design.rst
+++ b/docs/firmware-design.rst
@@ -2366,6 +2366,17 @@ This Architecture Extension is targeted when ``ARM_ARCH_MAJOR`` >= 8, or when
- The Compare and Swap instruction is used to implement spinlocks. Otherwise,
the load-/store-exclusive instruction pair is used.
+ARMv8.2
+~~~~~~~
+
+This Architecture Extension is targeted when ``ARM_ARCH_MAJOR`` == 8 and
+``ARM_ARCH_MINOR`` >= 2.
+
+- The Common not Private (CnP) bit is enabled to indicate that multiple
+ Page Entries in the same Inner Shareable domain use the same translation
+ table entries for a given stage of translation for a particular translation
+ regime.
+
Code Structure
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