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authorAchin Gupta <achin.gupta@arm.com>2014-07-18 18:38:28 +0100
committerAchin Gupta <achin.gupta@arm.com>2014-07-28 10:10:22 +0100
commitec3c10039bdc2c1468a8ba95fbbe9de78628eea5 (patch)
treeb8781fc14291cb3afd32a49ef8bbe5f60bdf0188 /bl32
parent539a7b383d52493a94df4f5da8f74aa102429fa0 (diff)
downloadtrusted-firmware-a-ec3c10039bdc2c1468a8ba95fbbe9de78628eea5.tar.gz
Simplify management of SCTLR_EL3 and SCTLR_EL1
This patch reworks the manner in which the M,A, C, SA, I, WXN & EE bits of SCTLR_EL3 & SCTLR_EL1 are managed. The EE bit is cleared immediately after reset in EL3. The I, A and SA bits are set next in EL3 and immediately upon entry in S-EL1. These bits are no longer managed in the blX_arch_setup() functions. They do not have to be saved and restored either. The M, WXN and optionally the C bit are set in the enable_mmu_elX() function. This is done during both the warm and cold boot paths. Fixes ARM-software/tf-issues#226 Change-Id: Ie894d1a07b8697c116960d858cd138c50bc7a069
Diffstat (limited to 'bl32')
-rw-r--r--bl32/tsp/aarch64/tsp_entrypoint.S12
1 files changed, 8 insertions, 4 deletions
diff --git a/bl32/tsp/aarch64/tsp_entrypoint.S b/bl32/tsp/aarch64/tsp_entrypoint.S
index 7a1797eef5..91b6128c55 100644
--- a/bl32/tsp/aarch64/tsp_entrypoint.S
+++ b/bl32/tsp/aarch64/tsp_entrypoint.S
@@ -89,11 +89,13 @@ func tsp_entrypoint
msr vbar_el1, x0
/* ---------------------------------------------
- * Enable the instruction cache.
+ * Enable the instruction cache, stack pointer
+ * and data access alignment checks
* ---------------------------------------------
*/
+ mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
mrs x0, sctlr_el1
- orr x0, x0, #SCTLR_I_BIT
+ orr x0, x0, x1
msr sctlr_el1, x0
isb
@@ -196,11 +198,13 @@ func tsp_cpu_on_entry
msr vbar_el1, x0
/* ---------------------------------------------
- * Enable the instruction cache.
+ * Enable the instruction cache, stack pointer
+ * and data access alignment checks
* ---------------------------------------------
*/
+ mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
mrs x0, sctlr_el1
- orr x0, x0, #SCTLR_I_BIT
+ orr x0, x0, x1
msr sctlr_el1, x0
isb