aboutsummaryrefslogtreecommitdiff
path: root/bl31
diff options
context:
space:
mode:
authorGerald Lejeune <gerald.lejeune@st.com>2016-03-22 09:29:23 +0100
committerGerald Lejeune <gerald.lejeune@st.com>2016-03-30 17:26:23 +0200
commitadb4fcfb4c515a9b9af68d386ed1350505480655 (patch)
tree9087d2aa75bc34f41290504025576434a1947786 /bl31
parent6b1ca8f35802fddc530e1a5f2be7b82ddbab6917 (diff)
downloadtrusted-firmware-a-adb4fcfb4c515a9b9af68d386ed1350505480655.tar.gz
Enable asynchronous abort exceptions during boot
Asynchronous abort exceptions generated by the platform during cold boot are not taken in EL3 unless SCR_EL3.EA is set. Therefore EA bit is set along with RES1 bits in early BL1 and BL31 architecture initialisation. Further write accesses to SCR_EL3 preserve these bits during cold boot. A build flag controls SCR_EL3.EA value to keep asynchronous abort exceptions being trapped by EL3 after cold boot or not. For further reference SError Interrupts are also known as asynchronous external aborts. On Cortex-A53 revisions below r0p2, asynchronous abort exceptions are taken in EL3 whatever the SCR_EL3.EA value is. Fixes arm-software/tf-issues#368 Signed-off-by: Gerald Lejeune <gerald.lejeune@st.com>
Diffstat (limited to 'bl31')
-rw-r--r--bl31/aarch64/bl31_arch_setup.c3
1 files changed, 0 insertions, 3 deletions
diff --git a/bl31/aarch64/bl31_arch_setup.c b/bl31/aarch64/bl31_arch_setup.c
index edf10188d3..0871b41959 100644
--- a/bl31/aarch64/bl31_arch_setup.c
+++ b/bl31/aarch64/bl31_arch_setup.c
@@ -43,9 +43,6 @@
******************************************************************************/
void bl31_arch_setup(void)
{
- /* Set the RES1 bits in the SCR_EL3 */
- write_scr_el3(SCR_RES1_BITS);
-
/* Program the counter frequency */
write_cntfrq_el0(plat_get_syscnt_freq());