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authordanh-arm <dan.handley@arm.com>2016-06-03 15:12:37 +0100
committerdanh-arm <dan.handley@arm.com>2016-06-03 15:12:37 +0100
commit8d8c61ea75d668ce4f13e5f7ebc5e56741b3f1bd (patch)
tree939fed21a2d2ddbb5dfec8234f5dff27e601078a /bl31
parenta7e530331d7cf4b58618f0715e61b5a872176f07 (diff)
parent8cd16e6b5b4a83a2cf704362b9acb1c2eea1417e (diff)
downloadtrusted-firmware-a-8d8c61ea75d668ce4f13e5f7ebc5e56741b3f1bd.tar.gz
Merge pull request #636 from soby-mathew/sm/cpu_ctx_rem_aarch32_regs
Build option to include AArch32 registers in cpu context
Diffstat (limited to 'bl31')
-rw-r--r--bl31/bl31_main.c13
1 files changed, 13 insertions, 0 deletions
diff --git a/bl31/bl31_main.c b/bl31/bl31_main.c
index 835d41e87b..7f04d2188c 100644
--- a/bl31/bl31_main.c
+++ b/bl31/bl31_main.c
@@ -145,6 +145,19 @@ void bl31_prepare_next_image_entry(void)
entry_point_info_t *next_image_info;
uint32_t image_type;
+#if CTX_INCLUDE_AARCH32_REGS
+ /*
+ * Ensure that the build flag to save AArch32 system registers in CPU
+ * context is not set for AArch64-only platforms.
+ */
+ if (((read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL1_SHIFT)
+ & ID_AA64PFR0_ELX_MASK) == 0x1) {
+ ERROR("EL1 supports AArch64-only. Please set build flag "
+ "CTX_INCLUDE_AARCH32_REGS = 0");
+ panic();
+ }
+#endif
+
/* Determine which image to execute next */
image_type = bl31_get_next_image_type();