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authorJeenu Viswambharan <jeenu.viswambharan@arm.com>2018-04-27 15:17:03 +0100
committerJeenu Viswambharan <jeenu.viswambharan@arm.com>2018-06-27 11:31:30 +0100
commit64ee263e20611fae9ddf0ee4a8fcfeb6fbc724ae (patch)
treef3207482f0c5ca18743a73d2568b81d4505722ff /bl31
parent92bec97f5c39b16b1599d41337ae4556b6da6c72 (diff)
downloadtrusted-firmware-a-64ee263e20611fae9ddf0ee4a8fcfeb6fbc724ae.tar.gz
DynamIQ: Enable MMU without using stack
Having an active stack while enabling MMU has shown coherency problems. This patch builds on top of translation library changes that introduces MMU-enabling without using stacks. Previously, with HW_ASSISTED_COHERENCY, data caches were disabled while enabling MMU only because of active stack. Now that we can enable MMU without using stack, we can enable both MMU and data caches at the same time. NOTE: Since this feature depends on using translation table library v2, disallow using translation table library v1 with HW_ASSISTED_COHERENCY. Fixes ARM-software/tf-issues#566 Change-Id: Ie55aba0c23ee9c5109eb3454cb8fa45d74f8bbb2 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
Diffstat (limited to 'bl31')
-rw-r--r--bl31/aarch64/bl31_entrypoint.S11
1 files changed, 4 insertions, 7 deletions
diff --git a/bl31/aarch64/bl31_entrypoint.S b/bl31/aarch64/bl31_entrypoint.S
index 0d1077cbd6..58e8afbd2f 100644
--- a/bl31/aarch64/bl31_entrypoint.S
+++ b/bl31/aarch64/bl31_entrypoint.S
@@ -170,15 +170,12 @@ func bl31_warm_entrypoint
* enter coherency (as CPUs already are); and there's no reason to have
* caches disabled either.
*/
- mov x0, #DISABLE_DCACHE
- bl bl31_plat_enable_mmu
-
#if HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY
- mrs x0, sctlr_el3
- orr x0, x0, #SCTLR_C_BIT
- msr sctlr_el3, x0
- isb
+ mov x0, xzr
+#else
+ mov x0, #DISABLE_DCACHE
#endif
+ bl bl31_plat_enable_mmu
bl psci_warmboot_entrypoint