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authorAntonio Nino Diaz <antonio.ninodiaz@arm.com>2019-01-31 11:58:00 +0000
committerAntonio Nino Diaz <antonio.ninodiaz@arm.com>2019-02-27 11:08:59 +0000
commit5283962ebaf77850d68bb457608ede5174e43159 (patch)
tree28fbac607b59b0d21cdef870f74afa5a78f274d9 /bl31
parent4d1ccf0ecc7d90df438148c633291723d095f979 (diff)
downloadtrusted-firmware-a-5283962ebaf77850d68bb457608ede5174e43159.tar.gz
Add ARMv8.3-PAuth registers to CPU context
ARMv8.3-PAuth adds functionality that supports address authentication of the contents of a register before that register is used as the target of an indirect branch, or as a load. This feature is supported only in AArch64 state. This feature is mandatory in ARMv8.3 implementations. This feature adds several registers to EL1. A new option called CTX_INCLUDE_PAUTH_REGS has been added to select if the TF needs to save them during Non-secure <-> Secure world switches. This option must be enabled if the hardware has the registers or the values will be leaked during world switches. To prevent leaks, this patch also disables pointer authentication in the Secure world if CTX_INCLUDE_PAUTH_REGS is 0. Any attempt to use it will be trapped in EL3. Change-Id: I27beba9907b9a86c6df1d0c5bf6180c972830855 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Diffstat (limited to 'bl31')
-rw-r--r--bl31/aarch64/ea_delegate.S10
-rw-r--r--bl31/aarch64/runtime_exceptions.S17
2 files changed, 24 insertions, 3 deletions
diff --git a/bl31/aarch64/ea_delegate.S b/bl31/aarch64/ea_delegate.S
index 0c8cfa8f92..d5ecfc50ee 100644
--- a/bl31/aarch64/ea_delegate.S
+++ b/bl31/aarch64/ea_delegate.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -68,6 +68,10 @@ func enter_lower_el_sync_ea
/* Save GP registers */
bl save_gp_registers
+#if CTX_INCLUDE_PAUTH_REGS
+ bl pauth_context_save
+#endif
+
/* Setup exception class and syndrome arguments for platform handler */
mov x0, #ERROR_EA_SYNC
mrs x1, esr_el3
@@ -98,6 +102,10 @@ func enter_lower_el_async_ea
/* Save GP registers */
bl save_gp_registers
+#if CTX_INCLUDE_PAUTH_REGS
+ bl pauth_context_save
+#endif
+
/* Setup exception class and syndrome arguments for platform handler */
mov x0, #ERROR_EA_ASYNC
mrs x1, esr_el3
diff --git a/bl31/aarch64/runtime_exceptions.S b/bl31/aarch64/runtime_exceptions.S
index 4f53b8e70d..cea7a8a1e8 100644
--- a/bl31/aarch64/runtime_exceptions.S
+++ b/bl31/aarch64/runtime_exceptions.S
@@ -120,7 +120,13 @@
* ---------------------------------------------------------------------
*/
.macro handle_interrupt_exception label
+
bl save_gp_registers
+
+#if CTX_INCLUDE_PAUTH_REGS
+ bl pauth_context_save
+#endif
+
/* Save the EL3 system registers needed to return from this exception */
mrs x0, spsr_el3
mrs x1, elr_el3
@@ -320,14 +326,21 @@ smc_handler32:
tbnz x0, #FUNCID_CC_SHIFT, smc_prohibited
smc_handler64:
+ /* NOTE: The code below must preserve x0-x4 */
+
+ /* Save general purpose registers */
+ bl save_gp_registers
+
+#if CTX_INCLUDE_PAUTH_REGS
+ bl pauth_context_save
+#endif
+
/*
* Populate the parameters for the SMC handler.
* We already have x0-x4 in place. x5 will point to a cookie (not used
* now). x6 will point to the context structure (SP_EL3) and x7 will
* contain flags we need to pass to the handler.
*/
- bl save_gp_registers
-
mov x5, xzr
mov x6, sp