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authorArd Biesheuvel <ard.biesheuvel@linaro.org>2019-01-06 10:07:24 +0100
committerArd Biesheuvel <ard.biesheuvel@linaro.org>2019-01-15 17:51:23 +0100
commit32e83537489267a8941f64caa58c0fa56d6b2c7e (patch)
tree51cfa41c09a5b609816d5e85230f86286e5a2b45 /bl31
parent0e4f761bc44346d0c08a8b272f148899198be825 (diff)
downloadtrusted-firmware-a-32e83537489267a8941f64caa58c0fa56d6b2c7e.tar.gz
spm: permit platform to override the VMA placement of the vector table
On some systems, it may be preferred to place the secure EL1/0 vector table outside of the static placement of the BL31 image itself, for instance when the latter is located in non-shareable SRAM which does not tolerate inner shareable WBWA mappings (as is the case on SynQuacer) So permit the platform to #define SPM_SHIM_EXCEPTIONS_VMA in its supplementary linker script, in which case it will be used as the VMA region for the vector table. Note that the LMA does not change, and it is up to the platform to copy the contents to the right place at init time. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Diffstat (limited to 'bl31')
-rw-r--r--bl31/bl31.ld.S9
1 files changed, 8 insertions, 1 deletions
diff --git a/bl31/bl31.ld.S b/bl31/bl31.ld.S
index 5925e0ca0c..c09b3517ef 100644
--- a/bl31/bl31.ld.S
+++ b/bl31/bl31.ld.S
@@ -143,6 +143,10 @@ SECTIONS
"cpu_ops not defined for this platform.")
#if ENABLE_SPM
+#ifndef SPM_SHIM_EXCEPTIONS_VMA
+#define SPM_SHIM_EXCEPTIONS_VMA RAM
+#endif
+
/*
* Exception vectors of the SPM shim layer. They must be aligned to a 2K
* address, but we need to place them in a separate page so that we can set
@@ -156,7 +160,10 @@ SECTIONS
*(.spm_shim_exceptions)
. = ALIGN(PAGE_SIZE);
__SPM_SHIM_EXCEPTIONS_END__ = .;
- } >RAM
+ } >SPM_SHIM_EXCEPTIONS_VMA AT>RAM
+
+ PROVIDE(__SPM_SHIM_EXCEPTIONS_LMA__ = LOADADDR(spm_shim_exceptions));
+ . = LOADADDR(spm_shim_exceptions) + SIZEOF(spm_shim_exceptions);
#endif
/*