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author | Scott Branden <sbranden@users.noreply.github.com> | 2017-04-29 08:36:12 -0700 |
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committer | GitHub <noreply@github.com> | 2017-04-29 08:36:12 -0700 |
commit | 0f22bef31d402e24fab77eb2a3c643d042b7e79c (patch) | |
tree | 6595ed7f87249ccbd4a953ba5cdc00963a130d18 /bl31 | |
parent | 53d9c9c85bc49845c4c40315e1ab29d627a1f8c3 (diff) | |
parent | dd454b40dfe42dbf77e2f04a3965295380b4f78d (diff) | |
download | trusted-firmware-a-0f22bef31d402e24fab77eb2a3c643d042b7e79c.tar.gz |
Merge branch 'integration' into tf_issue_461
Diffstat (limited to 'bl31')
-rw-r--r-- | bl31/aarch64/bl31_entrypoint.S | 31 | ||||
-rw-r--r-- | bl31/aarch64/crash_reporting.S | 4 | ||||
-rw-r--r-- | bl31/bl31_main.c | 5 |
3 files changed, 23 insertions, 17 deletions
diff --git a/bl31/aarch64/bl31_entrypoint.S b/bl31/aarch64/bl31_entrypoint.S index 623832900c..a847ae32d1 100644 --- a/bl31/aarch64/bl31_entrypoint.S +++ b/bl31/aarch64/bl31_entrypoint.S @@ -185,26 +185,27 @@ func bl31_warm_entrypoint * * The PSCI implementation invokes platform routines that enable CPUs to * participate in coherency. On a system where CPUs are not - * cache-coherent out of reset, having caches enabled until such time - * might lead to coherency issues (resulting from stale data getting - * speculatively fetched, among others). Therefore we keep data caches - * disabled while enabling the MMU, thereby forcing data accesses to - * have non-cacheable, nGnRnE attributes (these will always be coherent - * with main memory). + * cache-coherent without appropriate platform specific programming, + * having caches enabled until such time might lead to coherency issues + * (resulting from stale data getting speculatively fetched, among + * others). Therefore we keep data caches disabled even after enabling + * the MMU for such platforms. * - * On systems with hardware-assisted coherency, where CPUs are expected - * to be cache-coherent out of reset without needing explicit software - * intervention, PSCI need not invoke platform routines to enter - * coherency (as CPUs already are); and there's no reason to have caches - * disabled either. + * On systems with hardware-assisted coherency, or on single cluster + * platforms, such platform specific programming is not required to + * enter coherency (as CPUs already are); and there's no reason to have + * caches disabled either. */ -#if HW_ASSISTED_COHERENCY - mov x0, #0 -#else mov x0, #DISABLE_DCACHE -#endif bl bl31_plat_enable_mmu +#if HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY + mrs x0, sctlr_el3 + orr x0, x0, #SCTLR_C_BIT + msr sctlr_el3, x0 + isb +#endif + bl psci_warmboot_entrypoint #if ENABLE_RUNTIME_INSTRUMENTATION diff --git a/bl31/aarch64/crash_reporting.S b/bl31/aarch64/crash_reporting.S index 8e603862fd..c6d5c6c38f 100644 --- a/bl31/aarch64/crash_reporting.S +++ b/bl31/aarch64/crash_reporting.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -349,6 +349,8 @@ func do_crash_reporting /* Print some platform registers */ plat_crash_print_regs + bl plat_crash_console_flush + /* Done reporting */ no_ret plat_panic_handler endfunc do_crash_reporting diff --git a/bl31/bl31_main.c b/bl31/bl31_main.c index 85b3ea1e5f..c74b72b71c 100644 --- a/bl31/bl31_main.c +++ b/bl31/bl31_main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -33,6 +33,7 @@ #include <assert.h> #include <bl_common.h> #include <bl31.h> +#include <console.h> #include <context_mgmt.h> #include <debug.h> #include <platform.h> @@ -129,6 +130,8 @@ void bl31_main(void) */ bl31_prepare_next_image_entry(); + console_flush(); + /* * Perform any platform specific runtime setup prior to cold boot exit * from BL31 |