path: root/bl31/bl31.mk
diff options
authorAchin Gupta <achin.gupta@arm.com>2014-05-09 10:03:15 +0100
committerAchin Gupta <achin.gupta@arm.com>2014-05-22 17:46:56 +0100
commite1333f753f2760499ceed5c2d8f816574c3feb02 (patch)
treee3085f1eb529fd97b66f9deccf56bc0307f2b6cd /bl31/bl31.mk
parentc429b5e93202d6fed7b374c32f2ab0f1a139581d (diff)
Introduce interrupt registration framework in BL3-1
This patch introduces a framework for registering interrupts routed to EL3. The interrupt routing model is governed by the SCR_EL3.IRQ and FIQ bits and the security state an interrupt is generated in. The framework recognizes three type of interrupts depending upon which exception level and security state they should be handled in i.e. Secure EL1 interrupts, Non-secure interrupts and EL3 interrupts. It provides an API and macros that allow a runtime service to register an handler for a type of interrupt and specify the routing model. The framework validates the routing model and uses the context management framework to ensure that it is applied to the SCR_EL3 prior to entry into the target security state. It saves the handler in internal data structures. An API is provided to retrieve the handler when an interrupt of a particular type is asserted. Registration is expected to be done once by the primary CPU. The same handler and routing model is used for all CPUs. Support for EL3 interrupts will be added to the framework in the future. A makefile flag has been added to allow the FVP port choose between ARM GIC v2 and v3 support in EL3. The latter version is currently unsupported. A framework for handling interrupts in BL3-1 will be introduced in subsequent patches. The default routing model in the absence of any handlers expects no interrupts to be routed to EL3. Change-Id: Idf7c023b34fcd4800a5980f2bef85e4b5c29e649
Diffstat (limited to 'bl31/bl31.mk')
1 files changed, 1 insertions, 0 deletions
diff --git a/bl31/bl31.mk b/bl31/bl31.mk
index 6c9650f034..93a60c7696 100644
--- a/bl31/bl31.mk
+++ b/bl31/bl31.mk
@@ -31,6 +31,7 @@
BL31_SOURCES += bl31/bl31_main.c \
bl31/context_mgmt.c \
bl31/runtime_svc.c \
+ bl31/interrupt_mgmt.c \
bl31/aarch64/bl31_arch_setup.c \
bl31/aarch64/bl31_entrypoint.S \
bl31/aarch64/context.S \