aboutsummaryrefslogtreecommitdiff
path: root/bl31/aarch64/bl31_entrypoint.S
diff options
context:
space:
mode:
authorDavid Cunado <david.cunado@arm.com>2017-04-13 22:38:29 +0100
committerDavid Cunado <david.cunado@arm.com>2017-06-21 17:57:54 +0100
commit18f2efd67d881fe0a9a535ce9e801e60d746e024 (patch)
tree5c02488f3d5e7c29035e51f65fbe8b83fad74026 /bl31/aarch64/bl31_entrypoint.S
parentb1187232fdf819586ba8c8ece4a27a7515cbdc6d (diff)
downloadtrusted-firmware-a-18f2efd67d881fe0a9a535ce9e801e60d746e024.tar.gz
Fully initialise essential control registers
This patch updates the el3_arch_init_common macro so that it fully initialises essential control registers rather then relying on hardware to set the reset values. The context management functions are also updated to fully initialise the appropriate control registers when initialising the non-secure and secure context structures and when preparing to leave EL3 for a lower EL. This gives better alignement with the ARM ARM which states that software must initialise RES0 and RES1 fields with 0 / 1. This patch also corrects the following typos: "NASCR definitions" -> "NSACR definitions" Change-Id: Ia8940b8351dc27bc09e2138b011e249655041cfc Signed-off-by: David Cunado <david.cunado@arm.com>
Diffstat (limited to 'bl31/aarch64/bl31_entrypoint.S')
-rw-r--r--bl31/aarch64/bl31_entrypoint.S12
1 files changed, 6 insertions, 6 deletions
diff --git a/bl31/aarch64/bl31_entrypoint.S b/bl31/aarch64/bl31_entrypoint.S
index 6d10bce81b..419927d8eb 100644
--- a/bl31/aarch64/bl31_entrypoint.S
+++ b/bl31/aarch64/bl31_entrypoint.S
@@ -36,12 +36,12 @@ func bl31_entrypoint
* bl31_entrypoint() during the cold boot flow, so the cold/warm boot
* and primary/secondary CPU logic should not be executed in this case.
*
- * Also, assume that the previous bootloader has already set up the CPU
- * endianness and has initialised the memory.
+ * Also, assume that the previous bootloader has already initialised the
+ * SCTLR_EL3, including the endianness, and has initialised the memory.
* ---------------------------------------------------------------------
*/
el3_entrypoint_common \
- _set_endian=0 \
+ _init_sctlr=0 \
_warm_boot_mailbox=0 \
_secondary_cold_boot=0 \
_init_memory=0 \
@@ -62,7 +62,7 @@ func bl31_entrypoint
* ---------------------------------------------------------------------
*/
el3_entrypoint_common \
- _set_endian=1 \
+ _init_sctlr=1 \
_warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \
_secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \
_init_memory=1 \
@@ -136,7 +136,7 @@ func bl31_warm_entrypoint
* 'el3_entrypoint_common' must be skipped:
*
* - Only when the platform bypasses the BL1/BL31 entrypoint by
- * programming the reset address do we need to set the CPU endianness.
+ * programming the reset address do we need to initialise SCTLR_EL3.
* In other cases, we assume this has been taken care by the
* entrypoint code.
*
@@ -149,7 +149,7 @@ func bl31_warm_entrypoint
* it has been done once and for all on the cold boot path.
*/
el3_entrypoint_common \
- _set_endian=PROGRAMMABLE_RESET_ADDRESS \
+ _init_sctlr=PROGRAMMABLE_RESET_ADDRESS \
_warm_boot_mailbox=0 \
_secondary_cold_boot=0 \
_init_memory=0 \