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authorDan Handley <dan.handley@arm.com>2014-08-19 11:04:21 +0100
committerDan Handley <dan.handley@arm.com>2014-08-19 11:04:21 +0100
commita1d80440c44ce70e5fec4d8c60b5f6688b6cf8ff (patch)
tree27877c106f03eed314f529ee05e66cb747e1914b /bl2
parent57a18ff489fcfba38f26845eafacd90479c0be81 (diff)
parent0c8d4fef28768233f1f46b4d085f904293dffd2c (diff)
downloadtrusted-firmware-a-a1d80440c44ce70e5fec4d8c60b5f6688b6cf8ff.tar.gz
Merge pull request #189 from achingupta/ag/tf-issues#153
Unmask SError interrupt and clear SCR_EL3.EA bit
Diffstat (limited to 'bl2')
-rw-r--r--bl2/aarch64/bl2_entrypoint.S8
1 files changed, 8 insertions, 0 deletions
diff --git a/bl2/aarch64/bl2_entrypoint.S b/bl2/aarch64/bl2_entrypoint.S
index d3b0f558cf..2f058da9fc 100644
--- a/bl2/aarch64/bl2_entrypoint.S
+++ b/bl2/aarch64/bl2_entrypoint.S
@@ -53,6 +53,14 @@ func bl2_entrypoint
*/
adr x0, early_exceptions
msr vbar_el1, x0
+ isb
+
+ /* ---------------------------------------------
+ * Enable the SError interrupt now that the
+ * exception vectors have been setup.
+ * ---------------------------------------------
+ */
+ msr daifclr, #DAIF_ABT_BIT
/* ---------------------------------------------
* Enable the instruction cache, stack pointer