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author | Soby Mathew <soby.mathew@arm.com> | 2019-03-13 15:32:00 +0000 |
---|---|---|
committer | GitHub <noreply@github.com> | 2019-03-13 15:32:00 +0000 |
commit | c0ce16fba3365315fe2742f8fa96c0c259b42341 (patch) | |
tree | 0a3ef7624ad1dbca066dd58dd063de3464cb8832 /bl2 | |
parent | c61a807a4f93214504d9f2c942fa866c095202dd (diff) | |
parent | 02b57943965c89887170604e8eb801e17fd8cb99 (diff) | |
download | trusted-firmware-a-c0ce16fba3365315fe2742f8fa96c0c259b42341.tar.gz |
Merge pull request #1878 from jts-arm/sctlr
Apply stricter speculative load restriction
Diffstat (limited to 'bl2')
-rw-r--r-- | bl2/aarch32/bl2_entrypoint.S | 7 | ||||
-rw-r--r-- | bl2/aarch64/bl2_entrypoint.S | 4 |
2 files changed, 7 insertions, 4 deletions
diff --git a/bl2/aarch32/bl2_entrypoint.S b/bl2/aarch32/bl2_entrypoint.S index 23d1513565..102fd2f514 100644 --- a/bl2/aarch32/bl2_entrypoint.S +++ b/bl2/aarch32/bl2_entrypoint.S @@ -42,12 +42,13 @@ func bl2_entrypoint stcopr r0, VBAR isb - /* ----------------------------------------------------- - * Enable the instruction cache - * ----------------------------------------------------- + /* -------------------------------------------------------- + * Enable the instruction cache - disable speculative loads + * -------------------------------------------------------- */ ldcopr r0, SCTLR orr r0, r0, #SCTLR_I_BIT + bic r0, r0, #SCTLR_DSSBS_BIT stcopr r0, SCTLR isb diff --git a/bl2/aarch64/bl2_entrypoint.S b/bl2/aarch64/bl2_entrypoint.S index 611b8076df..c820cd1318 100644 --- a/bl2/aarch64/bl2_entrypoint.S +++ b/bl2/aarch64/bl2_entrypoint.S @@ -41,12 +41,14 @@ func bl2_entrypoint /* --------------------------------------------- * Enable the instruction cache, stack pointer - * and data access alignment checks + * and data access alignment checks and disable + * speculative loads. * --------------------------------------------- */ mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) mrs x0, sctlr_el1 orr x0, x0, x1 + bic x0, x0, #SCTLR_DSSBS_BIT msr sctlr_el1, x0 isb |